Patents by Inventor Donald E. Smeltzer

Donald E. Smeltzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for verifying design rule checks
    Patent number: 9934349
    Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 3, 2018
    Assignee: NXP USA, INC.
    Inventors: Inder Mohan Bhawnani, Ertugrul Demircan, Dwarka Prasad, Douglas M. Reber, Donald E. Smeltzer, Kenneth J. Danti
  • METHOD FOR VERIFYING DESIGN RULE CHECKS
    Publication number: 20160283642
    Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: INDER MOHAN BHAWNANI, ERTUGRUL DEMIRCAN, DWARKA PRASAD, DOUGLAS M. REBER, DONALD E. SMELTZER, KENNETH J. DANTI
  • Method and apparatus for indicating directionality in integrated circuit manufacturing
    Patent number: 7858487
    Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Mehul D. Shroff, Donald E. Smeltzer, Traci L. Smith
  • METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING
    Publication number: 20100112779
    Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 6, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: EDWARD O. TRAVIS, MEHUL D. SHROFF, DONALD E. SMELTZER, TRACI L. SMITH
  • Method and apparatus for indicating directionality in integrated circuit manufacturing
    Patent number: 7635920
    Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: December 22, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Mehul D. Shroff, Donald E. Smeltzer, Traci L. Smith