Patents by Inventor Donald Edward Steiss

Donald Edward Steiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817587
    Abstract: A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 27, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arthur John Redfern, Donald Edward Steiss, Timothy David Anderson, Kai Chirca
  • Patent number: 10810281
    Abstract: An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arthur John Redfern, Donald Edward Steiss, Mihir Narendra Mody, Tarek Aziz Lahlou
  • Publication number: 20180373678
    Abstract: An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.
    Type: Application
    Filed: August 7, 2018
    Publication date: December 27, 2018
    Inventors: Arthur John Redfern, Donald Edward Steiss, Mihir Narendra Mody, Tarek Aziz Lahlou
  • Patent number: 10114638
    Abstract: In one embodiment, command message generation and execution using a machine code-instruction is performed. One embodiment includes a particular machine executing a single machine-code instruction including a reference into a command-message-building data structure stored in memory. This executing the single machine-code instruction includes generating a command message and initiating communication of the command message to a hardware accelerator, including copying command information from the command-message-building data structure based on the reference into the command message. The hardware accelerator receives and executes the command message. In one embodiment, the command message is message-switched from a processor to a hardware accelerator, such as, but not limited to, a memory controller, a table lookup unit, or a prefix lookup unit. In one embodiment, a plurality of threads share the command-message-building data structure.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 30, 2018
    Assignee: Cisco Technology, Inc.
    Inventor: Donald Edward Steiss
  • Publication number: 20180246855
    Abstract: A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 30, 2018
    Inventors: Arthur John Redfern, Donald Edward Steiss, Timothy David Anderson, Kai Chirca
  • Patent number: 9798674
    Abstract: A page table is a data structure used by a virtual memory system in a computer system to store the mapping between virtual addresses and physical addresses. Embodiments herein use a tree to map a virtual memory address space in the page table. The tree may be an N-ary tree where N is a power of two (e.g., 2, 4, 8, 16, etc.). The tree may include multiple levels that each correspond to a different page table size. For example, an octree includes eight different entries for each child node which may include per-thread sub-entries. Child nodes in the first level of the octree may each correspond to a 512 GiB page, while child nodes in the second level, however, may each have eight entries that correspond to a 64 GiB page. In this manner, an N-ary tree may be used to support a computing system with varying page sizes.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 24, 2017
    Assignee: Cisco Technology, Inc.
    Inventor: Donald Edward Steiss
  • Patent number: 9519588
    Abstract: Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 13, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Donald Edward Steiss
  • Publication number: 20160170890
    Abstract: Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Inventor: Donald Edward STEISS
  • Publication number: 20160170896
    Abstract: A page table is a data structure used by a virtual memory system in a computer system to store the mapping between virtual addresses and physical addresses. Embodiments herein use a tree to map a virtual memory address space in the page table. The tree may be an N-ary tree where N is a power of two (e.g., 2, 4, 8, 16, etc.). The tree may include multiple levels that each correspond to a different page table size. For example, an octree includes eight different entries for each child node which may include per-thread sub-entries. Child nodes in the first level of the octree may each correspond to a 512 GiB page, while child nodes in the second level, however, may each have eight entries that correspond to a 64 GiB page. In this manner, an N-ary tree may be used to support a computing system with varying page sizes.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventor: Donald Edward STEISS
  • Publication number: 20160173601
    Abstract: In one embodiment, command message generation and execution using a machine code-instruction is performed. One embodiment includes a particular machine executing a single machine-code instruction including a reference into a command-message-building data structure stored in memory. This executing the single machine-code instruction includes generating a command message and initiating communication of the command message to a hardware accelerator, including copying command information from the command-message-building data structure based on the reference into the command message. The hardware accelerator receives and executes the command message. In one embodiment, the command message is message-switched from a processor to a hardware accelerator, such as, but not limited to, a memory controller, a table lookup unit, or a prefix lookup unit. In one embodiment, a plurality of threads share the command-message-building data structure.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventor: Donald Edward Steiss
  • Patent number: 9367470
    Abstract: Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: June 14, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Donald Edward Steiss
  • Patent number: 9256548
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, Jr., John H. W. Bettink, John C. Carney, Mark Warden Hervin
  • Publication number: 20150127911
    Abstract: Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: CISCO TECHNOLOGY, INC.
    Inventor: Donald Edward STEISS
  • Publication number: 20140149712
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, JR., John H. W. Bettink, John C. Carney, Mark Warden Hervin