Abstract: The parallelly arranged charge transfer channels in the image register of a field transfer type CCD imager are clocked with a number of phases equal to 2m, m being a positive integer equal to two or more, during image transfer. The successive gate electrodes receiving each cycle of successive-in-time clock phases during image transfer are considered to be consecutively ordinally numbered first through 2m.sup.th. During the image integration times of odd fields, the first gate electrode in each cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each first gate electrode. During the integration times of even fields, the (m+1).sup.th gate electrode in each gate-electrode cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each (m+1).sup.

Abstract: CCD imagers with pixels at least thirty microns long in the direction of charge transfer have their image registers forward clocked with at least five phases. The length of gate electrodes under which barrier are induced during image integration does not exceed the five to ten microns associated with acceptably low grain. Image integration takes place without applying voltages for inducing potential energy barrier to adjacent gate electrodes in the image register. These measures permit video signals with acceptably low grain to be obtained from these large-pixel images, solving a longstanding problem in the art.

Abstract: A cascade connection of first and second CCD shift registers having clocking signals with equal cycle durations, but with m phases and n phases respectively, where m is a larger positive integer than n.

Abstract: Grain, a fixed pattern noise which is not attributable just to dark current variations in the imager and which persists even in relatively bright images, is reduced in a CCD imager with three-phase-clocked imager register by introducing an offset potential between gate electrodes in the two clocking phases conventionally held at same potential during image integration times. In field transfer type CCD imagers, using field interlace and three-phase imager-register and field-store-register clocking, the offset potential can be made large enough, not only to reduce grain, but to improve field interlace from two-thirds field interlace towards or to perfect field interlace.

Abstract: Field-rate flicker is suppressed in a CCD imager having a three-phase operated image register provided interlacing by integrating odd-numbered fields with only the first clock phase high and even-numbered fields with only the second and third clock phases high. The flicker is suppressed by making the gate electrodes in the A register receiving the second and third clock phases of equal lengths, half that of the gate electrodes receiving the first clock phase.