Abstract: A plurality of integrated circuit wafers each having a plurality of cells disposed in a rectilinear array with the yield distribution of usable cells varying from wafer to wafer but in which there is a common yield distribution of at least Y usable cells or portions thereof in corresponding locations on N wafers (where Y and N are integers); a layer of electrical insulation that exposes the pads of the Y common yield distribution usable circuits to a second level of metalization which is formed into conductors by a first pad relocation mask which is common to the N wafers for effectively routing the exposed pads of the Y usable cells to master pattern circuit locations; and a layer of electrical insulation formed over the second level of metalization having master pattern vias formed therethrough which expose the pads at master pattern cell locations to a top layer of metalization formed into a common or master pattern of interconnects which interconnect the cells into the specific circuit type by a master pa

Abstract: A plurality of integrated circuit wafers each having a plurality of cells disposed in a rectilinear array with the yield distribution of usable cells varying from wafer to wafer but in which there is a common yield distribution of at least Y usable cells or portions thereof in corresponding locations on N wafers (where Y and N are integers); a layer of electrical insulation that exposes the pads of the Y common yield distribution usuable circuits to a second level of metalization which is formed into conductors by a first pad relocation mask which is common to the N wafers for effectively routing the exposed pads of the Y usable cells to master pattern circuit locations; and a layer of electrical insulation formed over the second level of metalization having master pattern vias formed therethrough which expose the pads at master pattern cell locations to a top layer of metalization formed into a common or master pattern of interconnects which interconnect the cells into the specific circuit type by a master p

Abstract: A complex integrated circuit comprising a wafer which has a plurality of cells each having signal-connect pads in a first layer of metalization on the wafer and which has an imperfect yield of usable cells.