Patents by Inventor Donald F. Faria

Donald F. Faria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making a high density programmable logic device in a multichip module package
    Patent number: 6642064
    Abstract: A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The prepackaged PLDs and the ability to use the substrate as a burn-in vehicle for the FPIC die results in reliable and reworkable assembly process with minimized yield loss.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: November 4, 2003
    Assignee: Altera Corporation
    Inventors: Richard S. Terrill, Donald F. Faria
  • Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
    Patent number: 6340897
    Abstract: A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: January 22, 2002
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria
  • Programmable logic array integrated circuit incorporating a first-in first-out memory
    Patent number: 6218860
    Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: April 17, 2001
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria
  • Programmable logic array integrated circuit incorporating a first-in first-out memory
    Patent number: 6134166
    Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: October 17, 2000
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria
  • Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
    Patent number: 6049223
    Abstract: A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: April 11, 2000
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria
  • Programmable logic array integrated circuit incorporating a first-in first-out memory
    Patent number: 5757207
    Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.
    Type: Grant
    Filed: May 6, 1996
    Date of Patent: May 26, 1998
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria
  • High-density programmable logic device in a multi-chip module package with improved interconnect scheme
    Patent number: 5642262
    Abstract: A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The input/output terminals of the PLDs are interconnected with the FPIC die in a scrambled fashion to reduce signal skew.
    Type: Grant
    Filed: February 23, 1995
    Date of Patent: June 24, 1997
    Assignee: Altera Corporation
    Inventors: Richard S. Terrill, Donald F. Faria
  • Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
    Patent number: 5572148
    Abstract: A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: November 5, 1996
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria
  • Programmable logic array integrated circuit incorporating a first-in first-out memory
    Patent number: 5570040
    Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: October 29, 1996
    Assignee: Altera Corporation
    Inventors: Craig S. Lytle, Donald F. Faria