Abstract: A method of forming a non-single-crystalline capacitor in an integrated circuit. It includes the steps of forming a first non-single-crystalline layer on a gate dielectric layer of a substrate of an integrated circuit. Next, a capacitor dielectric layer is formed on the first non-single-crystalline layer, and a second non-single-crystalline layer is formed on the capacitor dielectric layer. Portions of the second non-single-crystalline layer are removed to define a top plate of the capacitor. Portions of the capacitor dielectric layer are removed to define a dielectric of the capacitor. Also, portions of the first non-single-crystalline layer are removed to define the bottom plate of the capacitor.

Abstract: A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the N+ buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.

Abstract: A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the N+ buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.

Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations.

Abstract: A monolithic integrated circuit is mounted in a speaker cabinet to drive the voice coil of the speaker. The monolithic integrated circuit may be a class D amplifier and is at least a half bridge or full bridge power MOSFET device. Structures comprise MOS switching devices of the bridge driver and N+ buried layer of the QVDMOS transistors of the bridge circuits.

Abstract: Room temperature-testing of an MOS field effect transistor architecture, whose parameters have been optimized for operation at cryogenic temperatures, is facilitated by applying a prescribed reverse body-to-source voltage bias, that modifies the variation of the drain-to-source current vs. gate-to-source voltage characteristic, so as to shift the gate threshold voltage to a value corresponding to the device operating at its optimally designed cryogenic temperature. The magnitude of this back bias voltage is set at a value which adds to the number of charges required to balance the gate voltage before an inversion condition is achieved. In effect, the back bias causes the depletion layer beneath the gate to be expanded into the body beneath the gate, thereby compensating for what would otherwise be depletion mode operation, if the cryogenically designed MOS device were placed at room temperature.

Abstract: An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Abstract: A method for electrically isolating semiconductor devices in an integrated circuit structure with high field threshold, low defect level regions. The semiconductor structure includes a device layer predominantly comprising lattice silicon with a surface suitable for device formation. Multiple device regions are defined and field regions are defined for electrically isolating the device regions from one another. Dopant species are implanted to create a channel stop adjacent two of the device regions. The implant is of sufficient energy and concentration to impart within the device layer nucleation sites of the type known to result in stacking faults during oxide growth conditions. A thickness of thermally grown silicon dioxide is formed in the field regions by first thermally processing the integrated circuit structure to remove nucleation sites from the device layer and form a minor portion of the field oxide thickness.

Abstract: In a microelectronic device formed on a substrate 12, a pair of trenches 30, 36 branch at their intersection to provide branches 31-34 surrounding a sacrificial island 42. Sacrificial island 42 may comprise substrate material or other material or a void for absorbing the axial stresses propagated along the lengths of trenches 30, 36.

Abstract: Creation of structural defects in a trench-isolated island structure is obviated by protecting the bottom of the trench pattern during etching of the hard mask surface oxide. A layer of photoresist is non-selectively deposited on the hard mask oxide layer and in the trench pattern, so that the photoresist buffer layer fills the trench pattern and is formed atop the hard mask oxide layer. The deposited photoresist is controllably flood-irradiated, so as to expose the irradiated photoresist down to a depth in the trench pattern that is at or somewhat deeper than the surface of the hard mask insulating material. The exposed photoresist is then developed, so as to remove the irradiated depth portion of the photoresist lying atop the hard mask oxide layer and partially extending into the trench, thus exposing the hard mask oxide layer, but leaving a sufficient quantity of unexposed photoresist in the trench pattern that provides a surface barrier for the underlying oxide.

Abstract: A process of manufacturing a trench-isolated semiconductor structure comprises forming a first `pad` (e.g. MOS gate) oxide layer on a first surface of a silicon substrate. An oxide etch protective layer of silicon nitride is selectively formed on a first portion of the pad oxide layer so as to overlie a first surface portion of the silicon substrate in which active device regions will be introduced. A second oxide layer is then deposited on the pad oxide layer and on the nitride layer. The dual oxide layer is then patterned to form a trench mask which exposes a second surface portion of the silicon substrate. An etchant is then applied to the structure so as to etch away material from the silicon substrate exposed by the second surface portion and a portion of the second oxide layer, thereby forming a trench in the second surface portion of the silicon substrate.