Patents by Inventor Donald F. Weston

Donald F. Weston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ultra-thin die and method of fabricating same
    Patent number: 8198705
    Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 12, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
  • Ultra-thin die and method of fabricating same
    Patent number: 7507638
    Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
  • Plasma etch process for defining catalyst pads on nanoemissive displays
    Patent number: 7413924
    Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2008
    Assignee: Motorola, Inc.
    Inventors: Donald F. Weston, William J. Dauksher, Emmett M. Howard
  • Plasma etch process for multilayer vias having an organic layer with vertical sidewalls
    Patent number: 7125796
    Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: October 24, 2006
    Assignee: Motorola, Inc.
    Inventors: Donald F. Weston, William J. Dauksher, Ngoc V. Le