Patents by Inventor Donald Fowlkes

Donald Fowlkes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9269594
    Abstract: According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350 W/mK, an electrically insulating attached to the heat sink with an epoxy and a semiconductor chip attached to the heat sink on the same side as the lead frame with an electrically conductive material having a melting point of 280° C. or greater.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Anwar Mohammed, Julius Chew, Donald Fowlkes
  • Patent number: 8604609
    Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes, Alexander Komposch, Benjamin Pain-Fong Law, Michael Opiz Real
  • Patent number: 8314487
    Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 20, 2012
    Assignee: Infineon Technologies AG
    Inventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes, Alexander Komposch, Benjamin Pain-Fong Law, Michael Opiz Real
  • Patent number: 8258014
    Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Cynthia Blair, Donald Fowlkes
  • Publication number: 20120104582
    Abstract: According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350 W/mK, an electrically insulating attached to the heat sink with an epoxy and a semiconductor chip attached to the heat sink on the same side as the lead frame with an electrically conductive material having a melting point of 280° C. or greater.
    Type: Application
    Filed: January 5, 2012
    Publication date: May 3, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Anwar A. Mohammed, Julius Chew, Donald Fowlkes
  • Patent number: 8110915
    Abstract: An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative material separating the metallic regions from one another. The bottom surface of an RF semiconductor die is surface-mounted to the base region at the top substrate surface. The RF semiconductor die has a terminal pad disposed at a top surface of the RF semiconductor die. The terminal pad is electrically connected to one of the signal terminal regions at the top substrate surface. A lid is attached to the top substrate surface so that the RF semiconductor die is enclosed by the lid to form an open-cavity around the RF semiconductor die. The base and signal terminal regions are configured for surface-mounting at the bottom substrate surface.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: February 7, 2012
    Assignee: Infineon Technologies AG
    Inventors: Donald Fowlkes, Soon Ing Chew
  • Patent number: 8110445
    Abstract: According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/mK. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: February 7, 2012
    Assignee: Infineon Technologies AG
    Inventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes
  • Publication number: 20110258844
    Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.
    Type: Application
    Filed: June 30, 2011
    Publication date: October 27, 2011
    Applicant: Infineon Technologies AG
    Inventors: Cynthia Blair, Donald Fowlkes
  • Patent number: 7994630
    Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: August 9, 2011
    Assignee: Infineon Technologies AG
    Inventors: Cynthia Blair, Donald Fowlkes
  • Publication number: 20110147921
    Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes, Alexander Komposch, Benjamin Pain-Fong Law, Michael Opiz Real
  • Patent number: 7961470
    Abstract: An RF power amplifier including a single piece heat sink and an RF power transistor die mounted directly onto the heat sink.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: June 14, 2011
    Assignee: Infineon Technologies AG
    Inventors: Henrik Hoyer, Donald Fowlkes, Bradley Griswold
  • Publication number: 20110089529
    Abstract: An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative material separating the metallic regions from one another. The bottom surface of an RF semiconductor die is surface-mounted to the base region at the top substrate surface. The RF semiconductor die has a terminal pad disposed at a top surface of the RF semiconductor die. The terminal pad is electrically connected to one of the signal terminal regions at the top substrate surface. A lid is attached to the top substrate surface so that the RF semiconductor die is enclosed by the lid to form an open-cavity around the RF semiconductor die. The base and signal terminal regions are configured for surface-mounting at the bottom substrate surface.
    Type: Application
    Filed: October 16, 2009
    Publication date: April 21, 2011
    Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: Donald Fowlkes, Soon Ing Chew
  • Patent number: 7911041
    Abstract: A semiconductor device (7) has gold coatings (1 to 5) which are applied to metallic or ceramic components (6) of the semiconductor device (7). The gold coatings (1 to 4) have a multifunctional multilayer metal coating (8) with a minimal gold layer (9). The gold layer has a thickness dG where dG?0.5 ?m. Moreover, at least one metallic interlayer (10) is arranged between the gold layer (9) and the metallic or ceramic components (6).
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: March 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Jochen Dangelmaier, Donald Fowlkes, Volker Guengerich, Henrik Hoyer
  • Publication number: 20100283134
    Abstract: According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/m K. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater.
    Type: Application
    Filed: May 6, 2009
    Publication date: November 11, 2010
    Applicant: Infineon Technologies North America Corp.
    Inventors: Anwar A. Mohammed, Julius Chew, Donald Fowlkes
  • Publication number: 20100200979
    Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Applicant: Infineon Technologies North America Corp.
    Inventors: Cynthia Blair, Donald Fowlkes
  • Publication number: 20080019108
    Abstract: An RF power amplifier including a single piece heat sink and an RF power transistor die mounted directly onto the heat sink.
    Type: Application
    Filed: July 19, 2006
    Publication date: January 24, 2008
    Inventors: Henrik Hoyer, Donald Fowlkes, Bradley Griswold
  • Publication number: 20060175691
    Abstract: A semiconductor device (7) has gold coatings (1 to 5) which are applied to metallic or ceramic components (6) of the semiconductor device (7). The gold coatings (1 to 4) have a multifunctional multilayer metal coating (8) with a minimal gold layer (9). The gold layer has a thickness dG where dG?0.5 ?m. Moreover, at least one metallic interlayer (10) is arranged between the gold layer (9) and the metallic or ceramic components (6).
    Type: Application
    Filed: February 9, 2006
    Publication date: August 10, 2006
    Inventors: Jochen Dangelmaier, Donald Fowlkes, Volker Guengerich, Henrik Hoyer