Patents by Inventor Donald H. Friedberg

Donald H. Friedberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6320469
    Abstract: A method and lock detector for detecting lock between a reference signal and a feedback signal of a PLL circuit. A number of clock cycles of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock has been indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal indicating that lock has been achieved is provided if said qualification counter exceeds a qualification threshold.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: November 20, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Donald H. Friedberg, Dale Harvey Nelson, Lai Q. Pham
  • Patent number: 6194940
    Abstract: A clock switch controller has a clock status register which stores current clock data which identifies which of two or more clock signal sources is a current clock signal source currently in use as a system clock signal source. State machine logic of the controller automatically switches, in response to a clock switch signal, the system clock signal source from the current clock signal source to a new clock signal source of the two or more clock signal sources.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: February 27, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Michael James Hunter, Donald H. Friedberg
  • Patent number: 5974514
    Abstract: In a computer system having SDRAM memory banks that use a full burst read-modify-write operation as the sole mode for conducting memory operations, by selectively truncating the memory operation, it is possible to simulate either a burst read operation or a burst write operation. In a truncated read operation, a full read portion of the memory operation is performed. The tag is read with the first data line and is updated while the remaining lines of the burst are read. The tag is written using the write portion, but then the burst operation is aborted or truncated by issuing a precharge command to abort the write after the first line of the write is completed. This saves three clock periods out of a cycle of seventeen clock periods. A truncated write operation is similar to the read operation. A full burst read is started to retrieve the tag, which is stored to the first line, but the burst is truncated after the first line has been read.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: October 26, 1999
    Assignee: Hewlett-Packard
    Inventors: J. Michael Andrewartha, Donald H. Friedberg
  • Patent number: 5282210
    Abstract: A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: January 25, 1994
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Slegel, Charlotte A. Reed, Kirk D. Lamb, Donald H. Friedberg