Abstract: A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and are provided by the parallel-to-serial converter synchronous with an output clock signal. The input and output clock signals may have different frequencies, but the negative-going edges of each of these clock signals are synchronized to the negative-going edges of a master clock signal.

Abstract: An adaptive luma/chroma separation apparatus is herein disclosed. Means, including delay elements and bandpass filters, are employed to generate a set of three bandpassed signals B.sub.b, M.sub.b and T.sub.b, which are delayed with respect to each other by one horizontal line period. A control signal generating circuit coupled to receive the three bandpassed signals B.sub.b, M.sub.b and T.sub.b develops a control signal K that determines the relative mixing of the signals. A combining circuit, including a soft switch, combines the three bandpassed signals in response to the control signal K to generate a separated chroma signal C.sub.b. The separated chroma signal C.sub.b is subtracted from the (non-bandpassed) main signal M to generate the luma signal Y.

Abstract: A video features processor for use with a display device includes a first clock that is line locked to the display and a skew-shifted second clock that is phase locked to the horizontal sync component of an auxiliary video signal. An A/D converter, responsive to the skew-shifted clock, develops digital samples representative of the auxiliary video signal. A clock transfer circuit, responsive to the line-locked and skew-shifted clocks, translates digital samples occurring synchronously with the skew-shifted clock signal to digital samples occurring synchronously with the line-locked clock signal. The digital samples occurring synchronously with the line-locked clock signal are stored in a memory.

Abstract: An interpolating apparatus for generating a pair of non-identical, interlaced fields from a single stored field of video signal. One of the interlaced fields is generated by adding three-fourths of one line's amplitude to one-fourth of the next line's amplitude. The other interlaced field is generated by adding one-fourth of said one line's amplitude to three-fourths of the next line's amplitude.

Abstract: A picture-within-a-picture television receiver includes circuitry for displaying a reduced-size frozen image developed from an auxiliary signal as an inset in the main image. To develop signals representing two fields of the compressed auxiliary image, the system includes circuitry which processes first and second groups of successive horizontal line intervals of one field of the auxiliary video signal to develop signals representing mutually corresponding horizontal line intervals in two successive fields of the compressed auxiliary video signal.

Abstract: A frame comb filter includes a pair of serially-connected field memories. In the normal display mode, the first field memory stores one field of incoming composite video signal CVS and provides a field delayed video signal FDS. The second field memory stores one field of the field delayed video signal FDS and provides a frame delayed video signal FRS2. The incoming composite video signal CVS is combined with the frame delayed video signal FRS2 to generate a Y/C separated component luma signal CLS. In the zoom processing mode, the first field memory stores two fields or one frame of incoming composite video signal corresponding to the zoomed portion of the input image, and provides a frame delayed composite video signal FRS1 at its output. The incoming composite video signal CVS is combined with the frame delayed video signal FRS1 representative of the zoomed portion to produce a Y/C separated component luma signal CLS for the zoomed portion.

Abstract: A combination frame comb/freeze frame apparatus is disclosed. In the normal mode, the apparatus serves to separate one of the component signals (luma or chroma) from a composite video signal. In the freeze frame mode, the separated component signal is stored in the frame store, and repeatedly read out and displayed on the TV screen.

Abstract: Line and field deflection circuits generate line and field deflection currents in respective line and field deflection windings to scan a raster on the phosphor screen of a square-planar picture tube having an aspherical faceplate. The asphericity of the faceplate subjects the scanned raster to gullwing distortion. A gullwing distortion correction circuit is responsive to signals repeating at line and field rates, respectively, for modulating the field deflection current during a line deflection period within the field deflection trace interval in a manner that corrects gullwing distortion of a corresponding raster scan line.

Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.

Abstract: A periodic signal, at the frequency of the AC mains supply voltage, contains signal pulses, each having a duration that is substantially shorter than half the period of the AC mains supply voltage. The periodic signal is coupled to a high frequency transformer to form a periodic output signal that is applied to a time-of-day measurement circuit that provides time-of-day display information for a television receiver. The transformer provides conductive isolation between the time-of-day measurement circuit and the AC mains supply voltage source.

Abstract: In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to have jittering time bases that generally have prevented the use of such memory-based processing systems. The jittering signals may be standardized, in sampled data format, by effecting adaptive signal delays responsive to a measure of the relative phase of the sampling clock with respect to horizontal synchronizing pulses. The phase measure is used to control an interpolator which combines successive samples in proportions to develop sample values that should have occurred at the sample times had the signal not been jittering.

Abstract: A narrow bandwidth analog-to-digital conversion (ADC) system is described in the context of the color burst processing and burst phase detecting circuitry of a digital color television receiver. The ADC includes a dither generator which adds a dither signal to either the analog input signal or to the reference signal used by the ADC. This dither signal increases in magnitude by 1/16 of an LSB value at a rate one-quarter of the burst frequency and changes in sign at one-half of the burst frequency. This signal passes through a low-pass filter in the chrominance channel providing an increase in sample resolution by averaging the samples in a chroma band-pass filter and in the phase detecting circuitry.

Abstract: A motion adaptive recursive filter is modified to separate luminance or chrominance signal from composite video. The filter proportions and sums current and frame delayed signal recursively to provide signal-to-noise enhanced luminance signal with the chrominance component reduced to a steady state residual value the first frame after motion ceases. Current composite video signal is appropriately scaled and combined with the signal-to-noise enhanced signal to cancel the residual chrominance component therein.

Abstract: A horizontal deflection circuit output stage is coupled to a first end terminal of a primary winding of a flyback transformer for developing at that terminal a retrace voltage. A second end terminal of the primary winding is coupled to a switched mode power supply that provides at the second end terminal a combined voltage that is the sum of a DC B+ scanning voltage component and a horizontal rate rectangular-wave voltage component. The difference voltage between the retrace voltage and the rectangular-wave voltage component is developed between the end terminals of the primary winding of the flyback transformer and is coupled by transformer action to a high voltage secondary winding for generating an ultor accelerating potential. The phase of the rectangular-wave voltage component relative to the retrace voltage determines the level of the ultor accelerating potential.

Abstract: In a synchronized digital horizontal deflection system generating at 2xf.sub.H, a first word is produced that is indicative of the length of one-half the period H between f.sub.H rate horizontal sync pulses. A first f.sub.H rate signal that is synchronized to the horizontal sync pulses is generated. The first f.sub.H rate signal is time shifted by one-half of the period H, in accordance with the first word to produce a second f.sub.H rate second signal. The first and second signals are multiplexed for generating a horizontal deflection control signal at 2xf.sub.H rate that controls the retrace interval timing in a deflection circuit output stage.

Abstract: A speed-up memory converts interlaced RGB input signals to double line-rate (progressive scan) form. A vertical detail signal is derived from the RGB input signals before or after speed-up and a vertical peaking signal is derived from the detail signal. During the first read operation of the speed-up memory both signals are added to the speeded-up signals to effect a preshoot of the resultant signal and during the second speed-up memory read operation only the peaking signal added to affect an overshoot of the resultant signals whereby alternate lines of the converted RGB signals exhibit enhanced vertical detail.

Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses.

Abstract: In a synchronized digital horizontal deflection system operating at 2.times.f.sub.H, a digital phase-lock-loop circuit generates first f.sub.H rate signal that is synchronized to the horizontal sync pulses, and a second f.sub.H rate second signal that is delayed from the first signal by one-half of the period H. A digital phase-control-loop circuit receives the first and second signals and generates a horizontal deflection control signal at 2.times.f.sub.H rate that controls the retrace interval timing in a deflection circuit output stage. The synchronization of every other retrace interval occur in accordance with information provided by the first signal.

Abstract: In a digital video signal processing system including an image reproducing kinescope and a digital-to-analog converter (DAC), excessive kinescope beam current are automatically limited in response to a control signal which varies a reference voltage for the DAC such that the peak-to-peak amplitude of analog video signals from the DAC is reduced. A version of the control signal is applied to the output of the DAC with a magnitude and polarity for substantially negating unwanted shifts of the video signal black level during the beam current limiting mode.

Abstract: A digital sample rate reduction apparatus receives an input signal occurring at a given sample rate and produces an output signal occurring at a rate which is two-thirds the input sample rate. One half of the output samples are interpolated samples and the other half are original input samples.