Abstract: A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

Abstract: In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.

Abstract: A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

Abstract: Systems and methods are disclosed for supporting virtual microengines in a multithreaded processor, such as a microengine running on a network processor. In one embodiment code is written for execution by a plurality of virtual microengines. The code is than compiled and linked for execution on a physical microengine, at which time the physical microengine's threads are assigned to thread groups corresponding to the virtual microengines. Internal next neighbor rings are allocated within the physical microengine to facilitate communication between the thread groups. The code can then be loaded onto the physical microengine and executed, with each thread group executing the code written for its corresponding virtual microengine.

Abstract: A debugger tool that enables a user to perform packet-centric debugging in a network processor simulation environment is presented.

Abstract: A debugger tool that enables a user to set history marks at selected points in time in a simulation history and to navigate the history marks.

Abstract: A conditional breakpointing mechanism associates a breakpoint with a location in a program and with a breakpoint function that will be called to execute when the location is reached during a debugging session. The breakpoint function determines if a break will occur. The conditional breakpointing mechanism may used in a multi-threaded, multi-processor simulation environment.

Abstract: Method and apparatus to support a large Internet Protocol Forwarding Information Base. A packet is received at a network device, the packet including a destination address. A table is indexed into using a portion of the destination address to locate an entry in the table associated with the portion of the destination address. A pool index is derived from the portion of the destination address and is used to identify a pool of data blocks from among a plurality of pools of data blocks. The entry and the pool of data blocks are navigated to find a next-hop for the packet.

Abstract: A method and apparatus for meeting a given content throughput using at least one memory channel is generally described. In accordance with one example embodiment of the invention, a method to meet a given content throughput using at least one memory channel comprising, comparing the size of at least a portion of received content to a capacity of a single contiguous location within at least one memory channel to meet a given throughput and determining whether to distribute the at least portion of received content across the at least one memory channel, based at least in part, on the comparison.

Abstract: A tool that enables a user to perform instruction operand tracing during debug is presented. While executing microcode on a simulator, a history of register and memory values is saved. A graphic user interface uses these values to present a view of the microcode in a thread history. The user can use the thread history to select any given cycle time of the simulation, and switch over to a thread window (or code list view). The instruction that executed at the cycle of interest is marked in the code list view, and right-clicking on the code line, the user is given options, including an option to jump backward in time to the code line where a source variable was set and/or the option to jump forward in time to a code line that used a result variable.

Abstract: Method and apparatus for performing centralized cyclic redundancy checks (CRC). For one embodiment a current thread of execution compares a connection index with that of a previous thread of execution. If they share the same connection index, a CRC calculation may be performed without providing a CRC residue to a centralized CRC unit since the most recently produced CRC residue by would be associated with a preceding sequential cell of the same packet. For an alternative embodiment a current thread of execution requests a CRC calculation and provides a connection index to the centralized CRC unit, which is used to access a content addressable memory (CAM). A hit in the CAM indicates that the CRC unit may use the CRC residue associated with the connection index in the CAM since it would have resulted from a preceding sequential cell.

Abstract: A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.

Abstract: A scheduling mechanism to control transmission of data units, such as variable size packets or fixed size cells, to ports of a network device such as a switching fabric system. The scheduling mechanism maintains scheduling data structures, including an array storing information for available queues of ports and circular buffers representing nonempty port queues of the available port queues according to classes of service. The scheduling mechanism uses the data structures to make scheduling decisions concerning the scheduling of data units in the nonempty port queues for transmission to the ports.

Abstract: A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Abstract: In general, in one aspect, the disclosure describes a method of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first portion includes a set of least-significant bits and the second portion includes a set of more significant bits. The method also includes incrementing the first portion based on a packet and=determining if the incrementing of the first portion caused a designated bit of the first portion to be set. If it is determined that the incrementing of the first portion caused the designated bit to be set, the method increments the value stored by the second portion and resets the designated bit within the first portion.

Abstract: In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at least one thread to transmit packets received by the receive process. A scheduler process of at least one thread populates at least one schedule of flow service based, at least in part, on quality of service characteristics associated with the different flows. The schedule identifies different flow candidates for service. The system also includes a shaper process of at least one thread to select from the candidate flows for service from the at least one schedule.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.