Abstract: A micromechanical memory 100 element comprising a deflectable member 102 located between a first member 104 and a second member 106. The first member 104 is biased at a first member voltage, and the second member 106 is biased at a second member voltage. A bias voltage applied to the deflectable member will drive the deflectable member to either the first member 104 or the second member 106. A first contact 108 is positioned on the top, or end, of the first member 104. A second contact 110 is positioned on the top, or end, of the second member 106. These contacts are biased through resistors 112 and 114 with a first and second contact voltage sufficient to hold the deflectable member in place even after removal of the bias voltage applied to the deflectable member. The state of the micromechanical memory element can be determined by sensing the voltage of the deflectable member 102.

Abstract: A semiconductor memory device sensing circuit (400) is disclosed. The circuit includes a number of sense amplifiers (402), each of which is coupled to a first supply node (414) by a first driver device (P404-0 to P404-n), and to a second supply node (420) by a second driver device (N404-0 to N404-n). An increased driving current capability is provided by a number of first boost capacitors (C400) coupled between the first supply node (414) and an intermediate voltage (Vplate), and a number of second boost capacitors (C402) coupled between the second supply node (420) and the intermediate voltage (Vplate).

Abstract: A memory array (10) implemented by an integrated circuit is provided. The memory array (10) includes a bank of standard array cells (12) arranged in rows and columns. The bank of standard array cells (12) includes a plurality of rows of array cells (14) operable to provide memory storage and a plurality of rows of dummy cells (16) operable to provide a reference voltage level. A row decode block (22) is coupled to the bank of standard array cells via a plurality of wordlines (18) which include array cell wordlines and dummy cell wordlines. A sense amplifier block (24) is coupled to the bank of standard array cells (12) via a plurality of bitlines (20). The sense amplifier block (24) includes a plurality of sense amplifiers (26) coupled to the bitlines.

Abstract: A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit.

Abstract: A memory cell (10) comprises a ferromagnetic gate (12) disposed above a source (18) and a drain (20) in a substrate (16). A magnetic field is created in the ferromagnetic gate (12) by producing a large current between the source (18 ) and drain (20). The orientation of the magnetic field will depend upon the direction of the current flow. To read information from the memory cell (10), a small current is passed from source (18) to drain (20); if the electrons (25) are deflected upwards towards the surface (24) of the substrate (16), a lesser current will result than if the electrons (25) are deflected downward towards the bottom of the channel (22). Hence, the magnetic orientation, and therefore the information stored within the memory cell (10), can be determined by the amount of current detected.

Abstract: Hydrogen annealing permits deposition of good quality polysilicon atop TiO.sub.2. Hydrogen annealing of TiO.sub.2 prevents the tremendous hydrogen affinity of as-deposited TiO.sub.2 from disrupting process reactions during deposition of polysilicon.