Abstract: A radiation signal measurement system for millimeter wave transceivers is disclosed. Embodiments of the present invention utilize a laser to align the laser with an antenna. The transceiver is then moved into the path of the laser to align the laser with the transceiver. The transceiver or antenna orientation is changed such that the transceiver and antenna face each other, in an aligned position. Millimeter wave absorber material is applied to the inside and outside of the testing chamber to minimize reflections and interference from outside sources.

Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

Abstract: A radiation signal measurement system for millimeter wave transceivers is disclosed. Embodiments of the present invention utilize a laser to align the laser with an antenna. The transceiver is then moved into the path of the laser to align the laser with the transceiver. The transceiver or antenna orientation is changed such that the transceiver and antenna face each other, in an aligned position. Millimeter wave absorber material is applied to the inside and outside of the testing chamber to minimize reflections and interference from outside sources.

Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.

Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.

Abstract: An integrated circuit (IC) chip module includes at least one integrated circuit chip mounted upon a substrate, and a plurality of passive components mounted upon the substrate. A polymer based bib has at least one opening formed therein, the at least one opening configured to accommodate the at least one integrated circuit chip therein, and the bib further configured for attachment to one or more of the plurality of passive components. A protective cap is mounted over the at least one integrated circuit chip and attached to the substrate, wherein the bib is configured to retain thereon a thermally conductive paste initially applied to at least one of the integrated circuit chip and the protective cap.

Abstract: Instrumentation driver apparatus, including a main driver, coupled to receive an alternating input signal and having a main circuit structure, which is adapted to generate, in response to the alternating input signal, a main output signal with alternating voltage. The apparatus includes a mirror driver, coupled to receive a direct voltage input and having a mirror circuit structure located in proximity to the main circuit structure, which is adapted to generate a mirror output signal in response to the direct voltage input, such that a variation in an operating condition of the main driver causes a corresponding variation in the mirror output signal. The apparatus further includes a feedback circuit, coupled to receive the mirror output signal, which provides in response to the mirror output signal a feedback stabilization input to the main driver so as to stabilize the main output signal.

Abstract: A probe interface assembly connects a set of signal lines and a set of power lines from a circuit tester to one integrated circuit (IC) chip disposed among multiple circuit chips on a semiconductor wafer. The assembly includes a plurality of electrically conductive planes including metal mesh and conductive strips which are spaced apart by ceramic planes contiguous the conductive planes. The signal lines and the power lines enter the assembly with relatively large spacing at an input plane facing the tester, and exit the assembly with relatively small spacing at an output plane facing the chip. Within the assembly, each power line branches into a plurality of conducting vias for reducing resistance and inductance of the power lines. Connection of the vias to the power lines is accomplished by conductive planes near the output plane. Other ones of the conductive planes, near the input plane, interconnect input and output signal lines. Ground planes are interposed between power planes and signal planes.

Abstract: An integrated circuit test structure is comprised of a stacked substrate MLC space transformer (5). A top surface of an interface substrate (12) is employed for decoupling capacitor (36) placement. The top surface has metal conductors (20) exposed thereon for terminating power supply buses from a tester (1). Individual layers of a personalization substrate (14) are fabricated to redundantly extend internal power plane metalization (22) to the sidewalls. Redundant pads (26) are placed on each personalization layer to increase the surface area for side mount contact. Metal pads (18) are deposited over the exposed sidewall metal for forming a sidewall contact to the power planes within the personalization substrate.