Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word address lines and the bias lines for the capacitors are formed by metal strips. The gates of the access transistors and the capacitor gates are polysilicon. Metal-to-polysilicon contacts are made to connect the metal word lines to the polysilicon gates of the access transistors and to connect the metal bias lines to the capacitor gates.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Abstract: A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

Abstract: A semiconductor device of the MOS/LSI type uses a high speed serial shift register in its input/output system. In a memory device, the serial shift register has a number of stages equal to the number of columns in the memory cell array and is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.

Abstract: A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.

Abstract: A semiconductor memory device of the MOS/LSI type using an array of dynamic one-transistor cells has a high speed serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.

Abstract: A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides precise control of the delay over a wide range. Power dissipation is reduced in the driver circuit by avoiding the possibility of d.c. current paths when the reset clock goes high.

Abstract: A semiconductor integrated circuit functioning as a read only memory or ROM employs MOS diodes as the memory cells and is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Row address lines are metal strips and gates are polysilicon segments, while output or column lines are defined by elongated N+ regions. The gates are shorted to N+ drain regions to provide diode-like cells. Each MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide, rendering some cells of such high threshold that they will not turn on. Alternatively, the array may be contact programmable.

Abstract: A high speed address buffer circuit for use in MOS/LSI semiconductor memories or the like. An unbalanced, dynamic cross-coupled pair of MOS driver transistors is used to sense an address input during a short time window, and internal address signals are generated from the state of the sense circuit. Sensing nodes are precharged and equalized prior to the time window, and the node which is to stay at the logic "1" level is held at a high level by boosting capacitors to which a delayed clock signal is applied. The state of the sense circuit is sampled at a time after the delayed clock and high level addresses are generated.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have clock voltages applied to their gates after an initial sensing period, so the initial sensing is done without loads for the bistable circuit. After this initial period, the load transistors are turned on by boosting capacitors. Then, fixed biased transistors shunting the gates of the load device to the digit lines function to turn off the load device on the zero logic level side.

Abstract: Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.