Abstract: In one embodiment, an imager has an array of photodetectors, each of which accumulates charge during an integration period as a result of light detected during the integration period, the array having a charge capacity which increases during the integration period. A charge capacity controller coupled to the imager adjusts how the imager increases the charge capacity of the array based upon the brightness distribution detected by the imager during at least one previous integration period.

Abstract: An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients and an amorphans silicon a corbide layer.

Abstract: An extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.

Abstract: An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients.

Abstract: Pixel array including a high resolution mode and a low resolution mode and method of reading out the pixel array in a high and low resolution mode. The pixel array includes a first signal line and a second signal line. An array of pixel elements are provided, each pixel element coupled to the first signal line or the second signal line. A switch mechanism is provided for coupling the first signal line to the second signal line. A mechanism is also provided for conveying a charge associated with each pixel element to the first signal line or the second signal line. A mechanism may also be provided for buffering signals between the first signal line, the second signal line, and an output signal line.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract: A time-multiplexed floating diffusion output amplifier provides two output signals with different gains for each signal charge packet by dynamically controlling the floating diffusion capacitance using two external reset clocks. Two correlated double sampling circuits separately remove the noise components associated with resetting the two different floating diffusion capacitance values.

Abstract: The processor section comprises a matrix-line layout of processor units; each processor unit combined with adjacent processor units in row and column direction by means of IPC buses, which are two-way buses. The control/memory section comprises arrays of control/memory units corresponding one-to-one to the processor units; each control/memory unit entering instructions and data simultaneously to the corresponding units in the processor section via optical channels to carry out arithmetic operations. By providing grid-like buses on the control/memory-unit arrays, and transferring instructions and data on the buses and sending them to the processor unit corresponding one-to-one to the control/memory unit to which data are transferred via optical channels, the transfer of instructions and data is carried out efficiently between processor units beyond the third closest ones.

Abstract: In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.

Abstract: A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected and the phase-lock-loop circuit operates in an idle mode of operation.

Abstract: A constant impedance sampling switch suitable for a high-frequency analog-to-digital converter, presents a substantially constant impedance to the input signal regardless of the instantaneous level of the input signal. The exemplary sampling switch employs a single metal oxide semiconductor (MOS) transistor to selectively couple the input signal to a sampling circuit. The gate signal for this transistor is generated by circuitry which is disconnected from the gate of the transistor while the transistor is in an non-conductive state. During a sampling interval, the gate signal is boot-strapped by the instantaneous potential of the input signal to render the transistor conductive. Accordingly, the potential difference between the signal being sampled and the gate potential of the transistor remains substantially constant over a relatively wide range of amplitudes for the analog input signal.

Abstract: MIMD and pipeline processing is executed by entering data and control signals into processing chips in the form of optical signals, and entering multi-bit information (data and control signals) in parallel and at high speed on the basis of non-coherence of light beams. The efficiency of MIMD processing function has been improved by expanding data transfer buses between processors and output buses in place of data and control signal input buses that have become unnecessary. A processing chip for receiving optical signals consists of a large number of cells dedicated for vector computations, and/or a large number of cells dedicated for vector computations and/or cells dedicated for arithmetic and logical computations. A processing chip for wide applications ranging from vector computations to logical computations by employing a construction combining both processors.

Abstract: A voltage controlled oscillator (VCO) which may be adjusted to provide oscillatory signals for a wide range of frequencies includes a relaxation oscillator in which a ramp signal is compared to a reference threshold which exhibits hysteresis. The frequency of the oscillator is changed by varying the hysteresis range of the threshold level and by changing the rate at which the ramp is generated. At higher frequencies, the signal processing delay through the comparator is a factor in determining the frequency of the signal produced by the oscillator. Current sources internal to the oscillator are controlled by a reference potential that is generated from an externally supplied band-gap reference potential. The VCO is used in a phase-locked loop which includes a charge pump circuit that accumulates charge on a capacitor responsive to limited-width pulses applied to a current source which is controlled by the reference potential generated in the VCO.

Abstract: An auto-calibrated reference resistor ladder network is disclosed which is suitable for use in a precision analog to digital converter. Resistors in the ladder are connected to an auto-calibration circuit which continually measures the potential developed across each of the connected resistors and adjusts the resistance of the resistor to match the measured potential to a reference potential. In the disclosed circuit, the reference potential is the potential developed across a defined one of the resistors.

Abstract: In a pixel array having an array of pixel elements, a plurality of row select lines, a plurality of column select lines, and a plurality of signal lines, a pixel element is disclosed for minimizing dead space in an overall imager matrix which includes many pixel arrays. The pixel element includes a phototransducer device for detecting light, transmitting light or emitting light and a pair of series switching transistors coupled between the phototransducer device and a predetermined signal line. In addition, the pixel element includes at least one configurable transistor which is independent of the pair of switching transistors. This configurable transistor is interconnected with other configurable transistors from other pixel elements throughout the array in order to implement desirable functions, for example scanning circuitry, and amplification circuitry such that the dead space of each pixel array and, consequently, the overall imager array is minimized.

Abstract: An optical latch circuit is used for an optical-input section in a processor chip having a plurality of processor units each of which includes a processing section and an optical-input section. The optical input section includes a two-dimensional array, or matrix, of optical latch circuits. The optical latch circuit comprises a photodiode, coupled to a differential amplifier circuit having two CMOS circuits and a latch switch; a PMOS transistor of one of the CMOS circuits receives a control voltage from an auto-zero negative feedback circuit to produced threshold values by itself; and a PMOS transistor of the other CMOS circuit receives a control voltage from an optical-input stabilizing circuit, complementary to the auto-zero negative feedback circuit. The optical input of the photodiode is latched and amplified by turning on and off the latch switch in synchronism with the control clock, for transmission of digital electrical signals to input gates in the processing section.

Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto-calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good circuit yield and is compatible with ASICs.

Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good integrated circuit chip yield and is compatible with new ASICs.

Abstract: An X-Y addressable imager utilizes a gate connection of a source-follower-connected MOSFET to isolate inherent capacitance of each horizontal signal line of the imager from a vertical signal line that couples the MOSFETs to a common output circuit, including a load resistor for the source followers. In one embodiment the horizontal signal lines are assigned to different groups, and each group is coupled through a different one of plural vertical signal lines to the common output circuit. At least one multiplexer couples one vertical signal line at a time to the common output circuit. Also shown is imager array scanning logic for effecting variable integration of array pixels.