Abstract: A computer-implemented method of identifying sub-circuits in circuit designs includes: receiving a selection of a sub-circuit; specifying a match expression for the sub-circuit, where the match expression characterizes matching properties of components of the sub-circuit; modifying the match expression to change the matching properties of components of the sub-circuit; and producing an information structure in a computer readable medium, where the information structure associates a graph representing a topology of the selected sub-circuit with the modified match expression. Subsequently, the information structure corresponding to the selected sub-circuit can be identified in a given circuit design.

Abstract: A computer implemented method is provided for interactive application of constraints to sub-circuits in a circuit design stored in a computer readable medium, comprising: receiving from a first designer a selection of a sub-circuit; receiving from the first designer a constraint; producing an information structure in computer readable medium that associates a graph representing a topology of the selected sub-circuit with the received constraint; using the graph to identify sub-circuit instances in the circuit design having the same topology as the selected sub-circuit; receiving from a second designer a selection of the information structure; presenting to the second designer one or more of the identified sub-circuit instances and the received constraint; and receiving from the second designer instruction as to application of the received constraint to one or more of the presented sub-circuit instances.