Abstract: A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.

Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

Abstract: A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.

Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: A thin film resistor with an insulating layer disposed between a substrate material and a resistor material is disclosed. Also, disclosed is a technique for fabricating this thin film resistor. In accordance with the preferred embodiment, the thin film resistor employs an insulating layer of silicon nitride with a thickness of 2000 .ANG.. The insulating layer prevents the resistor layer from diffusing into the substrate material which, in turn, significantly reduces variations in the resistor value during accelerated life testing. Compared to thin film resistors with a resistor layer evaporated directly upon a substrate material, reliability is increased from a few hundred hours up to thousands of hours. Also, the maximum current handling capability is increased by greater than one order of magnitude, which results in a thin film resistor which requires less surface area of a wafer.

Abstract: Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate.

Abstract: A magnetic and electric force sensing method uses a force responsive transducer made of a micromachined, solid state magnetic sensor consisting of a central silicon platform surrounded and supported by a thin silicon membrane. The silicon substrate is placed over an aluminum pad recessed into a well on a supporting glass substrate. The magnetic sensor responds to a static method of measuring force whereby the Earth's magnetic field or magnetic field or other origin acts as an attractive or repulsive force towards the magnetic material placed onto the silicon platform. The magnetic force mechanically displaces the silicon platform and diaphragm membrane which is transduced to an electrical signal where a change in capacitance is measured. Geometry of the silicon platform, diaphragm membrane and glass well depth are used to affect the linearity, sensitivity and range of measurements of the magnetic sensor.

Abstract: This invention relates to force responsive transducers and more particularly concerns a micromachined, solid state micro-scale. The device consists of a central silicon platorm surrounded and supported by a thin silicon membrane. The silicon substrate is placed over an aluminum pad recessed into a well on a supporting glass substrate. The micro-scale responds to a static method of measuring force, similar to a spring scale. A gravitational acceleration vector acting on a mass placed onto the device produces a force known as weight. The weight mechanically displaces the silicon platform and membrane which is transduced to an electrical signal where a change in capacitance is measured. Geometry of the silicon platform, membrane and glass well depth may be used to affect the linearity, sensitivity and range of measurement of the micro-scale.