Abstract: A method of self-testing LSI circuits and/or systems in which LSI and discrete logic circuits are used that incorporates internally generated pseudorandom sequences as test vectors to stimulate the logic circuits under test. Responses to the test vectors are analyzed internally or externally using signature analysis to determine if the circuit has functioned properly. The method combines the best features of Level Sensitive Scan Design and prior art self-test methods to provide an efficient, easy to perform, self-test method that may be used at any testing level.