Patents by Inventor Donald Krall

Donald Krall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10148594
    Abstract: Systems and methods for an SDN switch that provides application-based conditional forwarding and session-aware load balancing are provided. According to one embodiment, a packet is received at an input port of a Software Defined Networking (SDN) switch. The packet is forwarded by the SDN switch to a first flow processing unit (FPU) of multiple FPUs of the SDN switch. The first FPU determines whether the packet is to be tracked. And, if so, the received packet is transmitted to a second FPU of the SDN switch; otherwise, the packet is transmitted to a third FPU of the SDN switch. When the packet is received at the second FPU, the packet is conditionally forwarded by the SDN switch to an application device. When the packet is received at the third FPU, the packet is conditionally forwarded to an output port or dropped.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: December 4, 2018
    Assignee: Fortinet, Inc.
    Inventors: Son Pham, Donald Krall, Venkateswara Adusumilli, Edward Lopez, Neil Huynh
  • Patent number: 10091166
    Abstract: Systems and methods for an SDN switch that provides service group chaining for sequentially serving multiple network security devices are provided. According to one embodiment, a packet received by the switch is processed by a first FPU based on a first set of rules and forwarded conditionally to a first security device. The packet is security processed, including dropping it or forwarding it to an egress port or forwarding it to a second FPU. When forwarded to the second FPU, the packet is processed based on a second set of rules by forwarding it to a second security device or dropping it or forwarding it to the egress port. When forwarded to the second security device, the packet is security processed, including dropping it or forwarding it to the egress port or conditionally forwarding it to a third FPU to be sequentially forwarded to a third security device.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: October 2, 2018
    Assignee: Fortinet, Inc.
    Inventors: Son Pham, Donald Krall, Venkateswara Adusumilli, Edward Lopez, Neil Huynh
  • Patent number: 10075393
    Abstract: Systems and methods for an SDN switch that facilitates forwarding/differential routing decision determination are provided. A packet is received at an input port of the SDN switch. The switch includes a first and second set of flow processing units (FPUs). The packet is forwarded to a first FPU of the first set. Based on a flow table associated with the first FPU, it is determined whether the packet is to be forwarded to a network device or an output port. The packet is received from the network device at a second FPU of the second set. Based on a flow table associated with the second FPU, it is determined whether to execute one or more instructions to forward the packet to the input or output port, or to drop or default forward the packet to the input or output port.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 11, 2018
    Assignee: Fortinet, Inc.
    Inventors: Son Pham, Donald Krall, Venkateswara Adusumilli, Edward Lopez, Neil Huynh
  • Publication number: 20170195255
    Abstract: Systems and methods for an SDN switch that facilitates forwarding/differential routing decision determination are provided. A packet is received at an input port of the SDN switch. The switch includes a first and second set of flow processing units (FPUs). The packet is forwarded to a first FPU of the first set. Based on a flow table associated with the first FPU, it is determined whether the packet is to be forwarded to a network device or an output port. The packet is received from the network device at a second FPU of the second set. Based on a flow table associated with the second FPU, it is determined whether to execute one or more instructions to forward the packet to the input or output port, or to drop or default forward the packet to the input or output port.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Applicant: Fortinet, Inc.
    Inventors: Son Pham, Donald Krall, Venkateswara Adusumilli, Edward Lopez, Neil Huynh
  • Publication number: 20170195292
    Abstract: Systems and methods for an SDN switch that provides service group chaining for sequentially serving multiple network security devices are provided. According to one embodiment, a packet received by the switch is processed by a first FPU based on a first set of rules and forwarded conditionally to a first security device. The packet is security processed, including dropping it or forwarding it to an egress port or forwarding it to a second FPU. When forwarded to the second FPU, the packet is processed based on a second set of rules by forwarding it to a second security device or dropping it or forwarding it to the egress port. When forwarded to the second security device, the packet is security processed, including dropping it or forwarding it to the egress port or conditionally forwarding it to a third FPU to be sequentially forwarded to a third security device.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Applicant: Fortinet, Inc.
    Inventors: Son Pham, Donald Krall, Venkateswara Adusumilli, Edward Lopez, Neil Huynh
  • Publication number: 20170195254
    Abstract: Systems and methods for an SDN switch that provides application-based conditional forwarding and session-aware load balancing are provided. According to one embodiment, a packet is received at an input port of a Software Defined Networking (SDN) switch. The packet is forwarded by the SDN switch to a first flow processing unit (FPU) of multiple FPUs of the SDN switch. The first FPU determines whether the packet is to be tracked. And, if so, the received packet is transmitted to a second FPU of the SDN switch; otherwise, the packet is transmitted to a third FPU of the SDN switch. When the packet is received at the second FPU, the packet is conditionally forwarded by the SDN switch to an application device. When the packet is received at the third FPU, the packet is conditionally forwarded to an output port or dropped.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Applicant: Fortinet, Inc.
    Inventors: Son Pham, Donald Krall, Venkateswara Adusumilli, Edward Lopez, Neil Huynh
  • Patent number: 9336748
    Abstract: The display of a portion of an image in successive rows of display tiles in a tiled display system are delayed, so that the top portion of a first display tile is illuminated immediately after the bottom portion of a second display tile is illuminated, where the second display tile is adjacent to and above the first display tile. This removes the appearance of a broken up image when the image moves across the display tiles in a direction somewhat parallel to the direction of raster scanning. In this way, a raster scanning tiled display system does not produce a stair-step effect even though the top and bottom portion of an image on a tile in the tiled display system is raster-scanned at different times.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: May 10, 2016
    Assignee: PRYSM, Inc.
    Inventors: Dimitrios Katsis, Donald A. Krall
  • Patent number: 8451195
    Abstract: Scanning beam display systems using fluorescent screens and various servo feedback control mechanisms to control display imaging qualities.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: May 28, 2013
    Assignee: Prysm, Inc.
    Inventors: Roger A. Hajjar, Alan C. Burroughs, Mark A. Pajdowski, David L. Kent, John Uebbing, Phillip H. Malyak, Donald A. Krall
  • Patent number: 8384625
    Abstract: Methods and systems for improving imaging quality and power efficiency of scanning beam display systems using fluorescent screens are disclosed. In various embodiments, beam shaping mechanisms for maximizing overlap between the beam cross-section and the florescent element corresponding to each color sub-pixel of the screen, as well as pulse width and timing adjustments, are introduced to reduce imaging noise and improve power efficiency of the display system.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 26, 2013
    Assignee: Prysm, Inc.
    Inventors: Roger A. Hajjar, Alan C. Burroughs, Mark A. Pajdowski, David L. Kent, John Uebbing, Phillip H. Malyak, Donald A. Krall
  • Patent number: 8379063
    Abstract: Techniques and devices use panels or screens with pixels for display or illumination applications to achieve dithered pixel brightness beyond pixel brightness levels set by a digital to analog conversion (DAC) circuit module with a preset DAC resolution between two adjacent DAC levels. In one implementation, when a pixel is to be dictated by a digital pixel signal to operate within an unstable brightness region, a control mechanism is provided to control the DAC circuit module to operate the pixel in the block at a DAC level below the unstable brightness region or at a different DAC level above the respective unstable brightness region, to achieve a perceived brightness level within the respective unstable brightness region.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: February 19, 2013
    Assignee: Prysm, Inc.
    Inventors: Anand Budni, Donald A. Krall
  • Publication number: 20120169777
    Abstract: Techniques and devices use panels or screens with pixels for display or illumination applications to achieve dithered pixel brightness beyond pixel brightness levels set by a digital to analog conversion (DAC) circuit module with a preset DAC resolution between two adjacent DAC levels. In one implementation, when a pixel is to be dictated by a digital pixel signal to operate within an unstable brightness region, a control mechanism is provided to control the DAC circuit module to operate the pixel in the block at a DAC level below the unstable brightness region or at a different DAC level above the respective unstable brightness region, to achieve a perceived brightness level within the respective unstable brightness region.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 5, 2012
    Applicant: PRYSM, INC.
    Inventors: Anand Budni, Donald A. Krall
  • Publication number: 20110074660
    Abstract: Methods and systems for improving imaging quality and power efficiency of scanning beam display systems using fluorescent screens are disclosed. In various embodiments, beam shaping mechanisms for maximizing overlap between the beam cross-section and the florescent element corresponding to each color sub-pixel of the screen, as well as pulse width and timing adjustments, are introduced to reduce imaging noise and improve power efficiency of the display system.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 31, 2011
    Applicant: PRYSM, INC.
    Inventors: Roger A. Hajjar, Alan C. Burroughs, Mark A. Pajdowski, David L. Kent, John Uebbing, Phillip H. Malyak, Donald A. Krall
  • Publication number: 20070188417
    Abstract: Scanning beam display systems using fluorescent screens and various servo feedback control mechanisms to control display imaging qualities.
    Type: Application
    Filed: September 1, 2006
    Publication date: August 16, 2007
    Inventors: Roger A. Hajjar, Alan C. Burroughs, Mark A. Pajdowski, David L. Kent, John Uebbing, Phillip H. Malyak, Donald A. Krall
  • Publication number: 20060193328
    Abstract: A network address filter that includes a random access memory configured to store network address data, a processor, and a comparator. The processor is configured to execute a hash function on input data to obtain a random access memory address that is applied to the random access memory to obtain network address data from the random access memory address. The comparator is configured to compare the input data to the network address data and indicate a match between the input data and the network address data.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 31, 2006
    Inventors: Ramana Rao, Russell Homer, Donald Krall
  • Patent number: 6510487
    Abstract: The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: January 21, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Anita X. Meng, Donald A. Krall, Khaldoon S. Abugharbieh, Roger J. Bettman
  • Patent number: 5821794
    Abstract: The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: October 13, 1998
    Assignee: Cypress Semiconductor Corp.
    Inventors: Hagop Nazarian, Donald A. Krall, S. Babar Raza
  • Patent number: 5710778
    Abstract: The present invention provides a circuit for supplying a verifying reference and measurement voltage for use in verifying the programming of a programmable cell. The present invention provides the verifying reference and measurement voltage through internal circuitry on the cell and eliminate any requirement for an externally provided reference voltage. The verifying voltage is provided by modifying the programming voltage. The programming voltage is stepped down or stepped up through the use of internal circuitry to provide the reference and measurement voltage.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: January 20, 1998
    Assignee: Cyrpress Semiconductor Corporation
    Inventors: Roger J. Bettman, S. Babar Raza, Donald Yu, Donald A. Krall, Anita X. Meng, Christopher S. Norris
  • Patent number: 5635856
    Abstract: A high-speed programmable macrocell includes structure sufficient to implement a combined in the combinatorial storage signal path when the macrocell is operated in the combinatorial, and storage modes of operation. The macrocell includes, a master circuit (including a polarity multiplexer), and a slave circuit (including a transmission gate). The polarity multiplexer is responsive to input data for generating an output signal corresponding to one of a true and complemented state of the input data, according to a polarity configuration bit. The master circuit stores the multiplexer output in response to a low-to-high transition of a clock signal when operating in the storage mode. The master circuit, when in the combinatorial mode, will always pass the multiplexer output therethrough.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: June 3, 1997
    Assignee: Cypress Semiconductor Corporation
    Inventors: S. Babar Raza, Donald Krall