Abstract: Access control to a high speed data buffer in a data processing machine is bypassed in order to enhance the speed of access of data which must be retrieved from a large capacity main storage facility without requiring additional circuitry in the data processing machine. Access control normally requires an entire line of data to be present in a cache before allowing a read to a portion of the line. When lines are moved in to the cache, only sub-line increments are loaded at a time. Thus, when a line is being moved in from a main store to the cache, the increment that satisfies a pending request for access is transferred first. The access control is overridden to allow access to the increment before the balance of the line is transferred.

Abstract: A memory apparatus which includes an intermediate store addressed by logical addresses and a main store addressed by system addresses. The memory unit has a translator for translating logical addresses to system addresses. The translator includes a translation lookaside buffer having a system address store with first and second fields storing system addresses corresponding to each translated logical address and a control field including a flipper bit for indicating which one of the system addresses is the currently active real address. The control field also includes an eviction pending bit for each system address field. When the TLB is updated with a new translation, the previos active address field is marked with an eviction pending bit and the the previos inactive address field is written over with the new translation and marked active.

Abstract: A data processing system includes virtual-addressed and real-addressed stores. Whenever an addressed location is not resident in the memory in which it is attempted to be accessed, the address is translated to the other address space. If a virtual address cannot access the desired location in the virtual memory the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real memory. Whenever a real address needs to access a virtual address in the virtual-addressed memory, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory. Virtual-to-real translation is carried out by storing the real addresses corresponding to a virtual address in a translation lookaside buffer. Entry to the translation lookaside buffer is gained by using a TLB pointer in a tag array which points to the TLB address which contains the desired real address.

Abstract: A memory system which comprises a mainstore for storing lines of data and a buffer store for storing lines of data that are a subset of the data stored in the main store. The buffer store is comprised of a plurality of associativities. A line of data stored in the buffer having a given address may be stored in any one of the plurality of associativities. A tag store stores a tag for the associativities. A field from a buffer store address is compared with the stored tag in the tag store to produce a data selection signal for selecting from among the plurality of associativities the proper line of data. When the buffer has only two associativities, a bit in the buffer store address which has different values for the two associativities is tested, and thus the proper line of data is selected. The bit position is indicated by a pointer stored in the tag array. A selection of one of two data lines is made prior to a determination of the presence or validity of data in the buffer store.

Abstract: Disclosed is a data processing system including virtual-addressed and real-addressed stores. One store is addressed with real addresses and the other store is addressed with virtual addresses. Whenever an addressed location is to be accessed in a store addressed by the other type of addresses, the address is translated to the other type of address. If a virtual address cannot access the desired location in the virtual store, the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real store. Whenever a real address needs to access a virtual address location in the virtual-addressed store, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory.

Abstract: Disclosed is an apparatus for storing data wherein there are at least two storage units which are addressed by different addressing schemes. The primary storage unit is addressed with a unique addressing scheme while the other storage units are addressed with a scheme wherein more than one of the other addresses may map to a single unique primary address. The apparatus for storing data includes a mechanism for translating all of the unique primary addresses to all of the other addresses which map to that unique primary address.

Abstract: A drum is adjustable in pitch by a pedal assembly connected by a wire cable to an actuating lever. The lever causes pressure to be exerted against a tension-adjusting ring over which the drumhead is stretched. The pedal may be locked in any selected position to maintain the desired pitch, and the height of the drum is adjustable without adjustment of the cable linkage. A drum which is adjustable in pitch by rotation of the drum shell can thus be made adjustable by use of a pedal as well. The assembly for exerting pressure against the tension-adjusting ring is designed to be retro-fitted to certain types of existing drums to permit use therewith without the need for extensive modifications.