Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.x Ga.sub.1-x As (106), next annealing out defects with the Al.sub.x Ga.sub.1-x As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.

Abstract: A method of fabricating a heterojunction bipolar transistor and the transistor by providing a substrate of a group III-V semiconductor material, doping a first selected region at a surface of the substrate a predetermined first conductivity type, concurrently or separately incorporating a group III element into a portion of the first selected region, doping the portion of the first selected region to a second conductivity type with a laser beam to cause melting and subsequent recrystallization of said substrate and forming contacts to the portion of the first selected region and to the first selected region. The portion of the first selected region extends farther into the substrate than the remainder of the first selected region. A complementary transistor can be concurrently fabricated using the same steps except that p-implants replace the n-implants and n-doped InGaAs instead of p-doped InGaAs forms the base layer.

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may be also be integrated on the substrate.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may also be integrated on the substrate.

Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.

Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small, isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectively grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirrors being the sidewalls of the vertical structures.

Abstract: A method of diffusion of dopants (e.g. zinc) into III-V substrates (e.g. GaAs) using metal silicide and dopants (e.g. W.sub.x Si.sub.y :Zn) is disclosed. A cap layer (e.g. SiO.sub.2 or Si.sub.3 N.sub.4) is also used. The zinc tungsten silicide is formed by cosputtering zinc and tungsten silicide (W.sub.5 Si.sub.3). Applications include adjustment of threshold voltages in JFETs by rapid thermal pulsing of zinc into device channel regions and use of the zinc tungsten silicide as a base contact plus extrinsic base dopant source together with a nitride sidewall self-alignment.

Abstract: A two step rapid thermal anneal (RTA) has been studied for activating Be implanted GaAs, where a short duration high temperature step is used to electrically activate the Be followed by a longer low temperature anneal for lattice re-growth. PN diodes show a substantial reduction in reverse diode leakage current after the lower temperature second step anneal, when compared to a single step RTA or to furnace annealing (FA). For low energy Be implants, no difference in electrical activation between the single step and the two step anneal is observed. Raman studies demonstrate that residual substrate impurities and high Be concentrations inhibit restoration of single crystal lattice characteristics after RTA. Lattice quality is also shown not to limit diode characteristics in the RTA material.