Abstract: A group of networked elements for controlling the equipment of a building, when the elements are in a learning mode, can be assembled by a pair of actions. The first action exerted by an installer on one of the elements should be interpreted as an interrogation concerning the state of membership in the group (for example, as included or excluded) of one of the elements of the group. The first action triggers the emission of an information signal regarding the identified element's state. The following, or second, action exerted on the chosen element is interpretable as an order for modifying the state of membership in the group of the chosen element.

Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: A processor is provided with a datapath and control logic to control the datapath to selectively effectuate execution of instructions of multiple ISA. In some embodiments, execution of the instructions of the different ISA are effectuated by selectively executing primitive operations (POP) of different ISA implementing POP collections. In some embodiments, the processor further includes at least one ISA selector accessible to the control logic to facilitate the control logic in controlling the datapath to selectively effectuate execution of the instructions of the different ISA. In some embodiments, the processor further includes an ISA library, storing and supplying, e.g. different collections of primitive operations implementing instructions of the different ISA, and logical to physical mappings of the different ISA.

Abstract: A processor is provided with a datapath and control logic to control the datapath to selectively effectuate execution of instructions of multiple ISA. In some embodiments, execution of the instructions of the different ISA are effectuated by selectively executing primitive operations (POP) of different ISA implementing POP collections. In some embodiments, the processor further includes at least one ISA selector accessible to the control logic to facilitate the control logic in controlling the datapath to selectively effectuate execution of the instructions of the different ISA. In some embodiments, the processor further includes an ISA library, storing and supplying, e.g. different collections of primitive operations implementing instructions of the different ISA, and logical to physical mappings of the different ISA.

Abstract: A pin control unit and a plurality of addressable storage locations are provided to an integrated circuit to control the input/output (I/O) pins of a functional block of the integrated circuit or the I/O pins of the integrated circuit. Multiple ones of the addressable storage locations are correspondingly coupled to I/O buffers associated with the I/O pins. The pin control unit selectively loads bit values into appropriate ones of the addressable storage locations. In response, the I/O buffers input bit values from and/or output bit values to the corresponding I/O pins. The pin control unit controls subsets of the I/O pins in a coordinated manner as I/O ports. The pin control unit also controls data movement between the addressable storage locations and various temporary storage elements of the functional block/integrated circuit.

Abstract: A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of the ISA. In one embodiment, primitive operations are statically organized into atomic units, which in turn are statically organized into snippets of execution threads. Selected ones of the snippets are logically associated together to form execution threads, which collectively implement the instructions of the ISA.

Abstract: A method and apparatus are provided for addressing a sequence of orderly spaced memory locations of a computer system, without requiring the address of each memory location to be retrieved from a register of the computer system. This is accomplished by storing at least part of the sequence into a cache memory of the computer system during a first operation referencing a first memory location within the sequence, detecting that a second operation references a second memory location within the sequence and retrieving the contents of the second memory location from the cache memory in parallel with calculating the memory address of the second memory location.

Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register sets to supply source operands and to accept destination operands for instruction execution. The different register sets may be of the same or of different virtual register files, and if the different register sets are of different virtual register files, the different virtual register files may be of the same or of different architectures. The cache locations implementing the registers may be directly accessed using cache addresses or content addressed using memory addresses.

Abstract: An apparatus employing a cache memory based approach to instruction execution includes a cache memory and one or more control units. The control units operate the cache memory to directly supply appropriate ones of a plurality of values stored in selected ones of said cache locations for a plurality of variables to one or more arithmetic logic units (ALU) as inputs to arithmetic/logic operations, and/or to directly accept and store results of arithmetic logic operations from the one or more ALU as values of the variables in selected ones of said cache locations. The direct supplying and the direct accepting and storing are performed responsive to instructions specifying said arithmetic/logic operations and logically designating the variables associated with the specified arithmetic/logic operations.

Abstract: A new datapath control logic for processors with ISA implemented employing hierarchically organized primitive operations is disclosed. The new datapath control logic includes a primary control unit (PCU) and at least one other auxiliary control unit (ACU). Together, the control units control the datapath of a processor to selectively execute hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of an ISA. Each instruction of the ISA is implemented with one or more hierarchical organization units of the hierarchically organized primitive operations. In one embodiment, the at least one other auxiliary control unit includes a first, a second and a third auxiliary control unit equipped to assist the primary control unit in dynamic decision variable evaluations, determining state transitions for contexts/processes comprised of threads of the hierarchically organized primitive operations, and controlling processor input/output.

Abstract: A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of the ISA. In one embodiment, primitive operations are statically organized into atomic units, which in turn are statically organized into snippets of execution threads. Selected ones of the snippets are logically associated together to form execution threads, which collectively implement the instructions of the ISA.

Abstract: A pin control unit and a plurality of addressable storage locations are provided to an integrated circuit to control the input/output (I/O) pins of a functional block of the integrated circuit or the I/O pins of the integrated circuit. Multiple ones of the addressable storage locations are correspondingly coupled to I/O buffers associated with the I/O pins. The pin control unit selectively loads bit values into appropriate ones of the addressable storage locations. In response, the I/O buffers input bit values from and/or output bit values to the corresponding I/O pins. The pin control unit controls subsets of the I/O pins in a coordinated manner as I/O ports. The pin control unit also controls data movement between the addressable storage locations and various temporary storage elements of the functional block/integrated circuit.

Abstract: A processor is provided with a number of control registers logically organized in a hierarchical manner. At the highest level is a set of control registers for controlling the overall system. At the second highest level are multiple sets of control registers for controlling concurrent execution of processes in multiple contexts. At the third highest level are multiple sets of control registers for controlling concurrent execution of multiple process threads for each of the concurrently executing contexts. Besides modifications resulting from the normal course of instruction execution, the control registers are directly accessible and modifiable using instructions of the standard instruction set. Each context/thread is assigned a variable privilege level for accessing and modifying control registers at the various levels. The instruction fetch unit is enhanced to dispatch instructions with appended context and tag identifications.

Abstract: An improved prefetch program counter (PC) generation circuitry is provided to the prefetch and dispatch unit (PDU) of a pipelined computer system. The prefetch PC generation circuitry factors into consideration the states of dispatched CTIs in various pipeline stages, when generating a new prefetch PC value for instruction prefetching. The dispatched CTI state dependent prefetch PC generation circuitry includes storage circuitry, fetch control circuitry, and fetch PC generation circuitry. Together, the storage circuitry, the fetch control circuitry, and the fetch PC generation circuitry cooperate to prefetch instructions in a CTI state dependent manner, thereby improving the instruction prefetch rate. In one embodiment, two dynamically switchable instruction fetch queues are provided, with one being used as the sequential instruction fetch queue, and the other being used as the target instruction fetch queue.

Abstract: The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.