Abstract: In described embodiments, a data communication device employing, for example, a modem and a data access arrangement (DAA) electrically connected to a telephone network has an increased surge immunity through use of improved hook switch driver and line modulation driver circuitry. In accordance with described embodiments, hook switch driver circuitry exhibits decreased surge power dissipation by maintaining the hook switch driver transistors in saturation at higher currents while reducing the collector-emitter voltage across hook switch driver transistors, and line modulation driver circuitry exhibits decreased total surge power dissipation by i) limiting surge voltage ii) over voltage stress of the line driver transistor.

Abstract: In described embodiments, a data communication device employing, for example, a modem and a data access arrangement (DAA) electrically connected to a telephone network has an increased surge immunity through use of improved hook switch driver and line modulation driver circuitry. In accordance with described embodiments, hook switch driver circuitry exhibits decreased surge power dissipation by maintaining the hook switch driver transistors in saturation at higher currents while reducing the collector-emitter voltage across hook switch driver transistors, and line modulation driver circuitry exhibits decreased total surge power dissipation by i) limiting surge voltage ii) over voltage stress of the line driver transistor.

Abstract: The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

Abstract: The invention provides a low cost, simple, circuit for detecting the condition of a telephone line.

Abstract: The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.

Abstract: The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling clocks, with these clocks having sampling clock phases separated in time. These clocks are used in conjunction with multiple data detectors and phase detectors to efficiently process received analog signals in a decimated loop filter system.

Abstract: A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.

Abstract: In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.