Abstract: Disclosed are post-fermentation methods for altering a base beer to taste like and have an appearance similar to a target beer, which include analyzing and comparing the beer style characteristics of the target beers and adding style changing ingredients or substances to the base beer. Also disclosed are target beers comprising base beers that have been altered to taste similar to and have an appearance similar to a target beer. Further disclosed are novel distribution methods for a plurality of beer styles using one or few base beer styles.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: Disclosed is transmission of a signal over a single interconnect between functional blocks of the IC. A scaled or encoded signal responsive to a first digital signal is generated by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

Abstract: A CMOS negative voltage generator is provided which uses N-well technology. A positive voltage generator charges a load capacitor to a doubled voltage level. A first cycle of operation charges an output capacitor to a potential equal to the difference between the doubled voltage and the original voltage source. A second cycle of operation references the previously positive reference node of the output capacitor to ground level, and lets the negative node of the capacitor float to a potential equal in magnitude to the original power source, however now being negative with reference to ground. The negative voltage generator is ideal for driving a low impedance p-channel MOSFET. The negative voltage generator is ideal in low voltage circuits, including those with three volt supplies.

Abstract: The present invention provides a method and apparatus to save area of an IC. Included in the present invention is a method of transmitting an signal over a single interconnect between functional blocks of the IC. The method includes generating a scaled or encoded signal responsive to a first digital signal by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: The present invention includes a charge pump that has an advantageous use in a phase-lock loop. The charge pump includes a current mirror, at least two switches and a loop. The current mirror pumps up loop filters according to input signals. The loop senses the common mode of loop filter nodes and compares them to a reference voltage. If the common mode is not at a desired level, then the loop provides leakage paths that are turned on to bring the nodes to that desired level. The use of the current mirror substantially reduces current mismatch. Furthermore, the loop is active for a relatively short time, thus minimizing the introduction of any errors. The present invention reduces static phase error by reducing current mismatch.

Abstract: A method and apparatus for providing a constant output power supply that is different from a system power supply. A system power supply voltage is sensed and compared to a predetermined output voltage value. If the supply voltage is greater than the voltage value, the supply voltage is decreased, such as through regulation. If the supply voltage is less than the votlage value, the supply voltage is increased, such as through charge pumping. The apparatus is preferably coupled between a system power supply and a circuit that operates on a voltage that is different from the supply voltage.

Abstract: An on-chip driver is described for applications voltage output signals are desired from a digital sub-micron CMOS integrated circuit. The driver includes a signal buffer, signal level shifter, output pull-up, and an output pull-down. The signal buffer is coupled to a digital CMOS input for generating a corresponding buffered signal that is received by both the output-up down and the level shifter. The output pull-down is responsive to the buffered signal and operates to pull the output of the driver to a low voltage level of about 0 volts when the digital CMOS input is at a low logic state. Further, the level shifter is responsive to the buffered signal for generating a voltage shifted signal that is received by the pull-up which pulls the output of the driver to a high voltage level of 2.5 volts or greater when the digital CMOS input is at a high logic state.

Abstract: An integrated circuit includes a substrate and at least two circuits, such as a digital circuit and an analog circuit. The substrate is preferably derived from a bulk substrate wafer. The integrated circuit preferably comprises at least two islands in the substrate for noise isolation between the circuits. The two islands are buried-layers that are implanted, by preference, using conventional MeV techniques. A method of manufacturing an integrated circuit includes a substrate and at least two circuits. The method comprises the step of implanting at least two islands in the substrate for noise isolation between the circuits. The implanting is accomplished by conventional masking and high-energy implantation, such as MeV.

Abstract: The invention concerns an adaptive driver circuit which can source and sink current when powered by different power supply voltages. The invention maintains the output voltage substantially constant, for a given load, when the voltage of the power supply changes.

Abstract: The invention concerns battery back-up for electronic equipment. A sensor detects a drop in power supply voltage and, in response, connects the back-up battery to the equipment, via a Field-Effect Transistor (FET). The FET causes a lower voltage drop between the battery and the equipment, as compared with a commonly used alternative, namely, a diode.

Abstract: A CMOS disk drive motor control circuit which has back-EMF regulator circuitry which prevents the back-EMF from the disk drive motor from exceeding a predetermined level. The back-EMF provides an alternate power source for parking the read/write head when power is removed from the disk drive. The circuit is fabricated as a single CMOS integrated circuit which is coupled between a power supply and the disk drive motor. The disk drive control circuit also includes a blocking diode through which power from the power supply flows to the motor and which prevents dissipation of a back-EMF from the motor when power is removed from the motor, and disk drive head parking circuitry which uses the back-EMF to retract and park the disk drive head.

Abstract: A CMOS disk drive motor control circuit which has back-EMF blocking circuitry for preventing the back-EMF from being dissipated when power is removed from the disk drive motor. The back-EMF provides an alternate power source for parking the read/write head. The circuit is fabricated as a single CMOS integrated circuit which is coupled between a power supply and the disk drive motor. The circuit also includes disk drive head parking circuitry and voltage regulator circuitry.

Abstract: A voltage controlled current source including feedback circuitry which eliminates the need for a current sensing resistor in series with the output voltage controlled current source. The feedback circuit includes circuitry for generating a reference current which is proportional to, but much smaller than, the output current produced by the current source, and current mirror circuitry for generating a sense current which is equivalent to the reference current. The sense current is provided to a current sense resistor, across which a feedback voltage is developed. The voltage controlled current source further includes an amplifier connected to receive an input control voltage and the feedback voltage for generating the output current in response to the input control voltage and the feedback voltage.

Abstract: A CMOS motor drive for a disk drive spindle motor. The design of the drive circuit permits the integration of power electronics together with logic or other circuitry on a single integrated circuit wafer. For each motor phase the power electronics formed on the integrated circuit wafer includes a plurality of P-type and N-type MOSFET power transistor pairs and a plurality of corresponding output bonding pads; the drain terminals of each transistor pair being connected together to its corresponding output bonding pad. The wafer is enclosed in packaging which includes an output pin for providing an electrical connection to one phase of the disk drive spindle motor, and a plurality of bond wires corresponding to the plurality of output bonding pads, each bond wire providing an electrical connection between its corresponding bonding pad and the output pin. The transistor pairs and bond wires operate in parallel, each carrying an equivalent portion of the total current output presented at the output pin.

Abstract: The invention concerns utilization of a single pin on an integrated circuit for a dual purpose. First, the pin carries data in a normal manner. Second, the pin carries a test signal, which is used, for example, to trigger a testing circuit into action. The invention receives both the data signals and the test signal. The invention ignores the data signals, and responds only to the test signals.

Abstract: A biasing system for a CMOS differential comparator includes a unity gain amplifier for developing a reference voltage corresponding to the trip point of an output inverter. The reference voltage is applied to a voltage to current converter for developing a reference current proportional to the reference voltage. The reference current biases the output inverters at their trip points when the input voltages to the differential comparator are at the same potential. The biasing system includes a reference inverter having characteristics substantially identical to the output inverters. The output and input of the reference inverter are connected together so that a reference voltage is established at the inverter output which is always at the switch point of the inverter. A differential transistor stage includes resistive loads matched in process characteristics and sized to each pass one-half the value of the reference current to reduce the load capacitance at the differential stage.