Abstract: Systems and methods for compositing an image directly from multiple source image data for reducing system memory footprint and bandwidth and for improving color quality of the image. The image is divided into spans, lines, and slices. Each line includes at least one span and each slice includes at least one line. All lines in a slice have spans associated with identical sources. An image is composited by reading the image data directly from one or more sources of each span. If necessary, the sources are blended. A control structure is used to provide the image context and identifies the sources of the spans. The control structure includes headers for each data stream from each source of each span. Also, the color quality of the image is improved by reducing the number of color space conversions that occur as the image is composited. All sources in the same color space are blended before being blended with sources from other color spaces. Preferably, no more than a single color conversion is required.

Abstract: Systems and methods for compositing an image directly from multiple source image data for reducing system memory footprint and bandwidth and for improving color quality of the image. The image is divided into spans, lines, and slices. Each line includes at least one span and each slice includes at least one line. All lines in a slice have spans associated with identical sources. An image is composited by reading the image data directly from one or more sources of each span. If necessary, the sources are blended. A control structure is used to provide the image context and identifies the sources of the spans. The control structure includes headers for each data stream from each source of each span. Also, the color quality of the image is improved by reducing the number of color space conversions that occur as the image is composited. All sources in the same color space are blended, before being blended with sources from other color spaces. Preferably, no more than a single color conversion is required.

Abstract: Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.

Abstract: Real-time communication of multimedia data over heterogeneous networks that may include constant delay networks, variable delay networks that have a common reckoning of time, and variable delay networks that do not have a common reckoning of time. If there are any variable delay networks in which there is no common reckoning of time in the heterogeneous networks, a common reckoning of time is established in each of those networks. Then, a constant delay network is emulated for each variable delay network using the specific common time reckoning present in each variable delay network.

Abstract: The present invention is directed to a method and system for disaggregating and connecting A/V components, and communicating A/V content stream information. An A/V stream from a source device is packaged for transmission over an IP network to one or more output devices. A brick device enables the integration of legacy A/V systems into the network supported A/V system. The brick device operates to provide analog signal and IP protocol conversion, along with the synchronization of received A/V stream data packets. The rendering and play of the A/V stream content on multiple output devices is synchronized to overcome distortions and other network idiosyncrasy and to facilitate a pleasant user experience.

Abstract: A radio module that detachably connects with a host device. A radio module is provided that includes an antenna as an integral part of the radio module. The antenna satisfies regulatory requirements by being an integral part of the radio module. The radio module includes an interface circuit that provides the processing required for communication over a wireless network. The functionality of the interface can be divided between the radio module and the host device. The physical interface between a host device and the radio module may depend on which functions are implemented by the radio module and which functions are implemented by the host device. In one example, the physical interface is a standard connection that permits the radio module to be detachably connected with multiple devices. The radio module also includes a flexible cable such that the radio module can be optimally positioned within the wireless network.

Abstract: A radio module that detachably connects with a host device. A radio module is provided that includes an antenna as an integral part of the radio module. The antenna satisfies regulatory requirements by being an integral part of the radio module. The radio module includes an interface circuit that provides the processing required for communication over a wireless network. The functionality of the interface can be divided between the radio module and the host device. The physical interface between a host device and the radio module may depend on which functions are implemented by the radio module and which functions are implemented by the host device. In one example, the physical interface is a standard connection that permits the radio module to be detachably connected with multiple devices. The radio module also includes a flexible cable such that the radio module can be optimally positioned within the wireless network.

Abstract: Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.

Abstract: A new network connection setup procedure for network computers to set up data transmission connections over a network that implements traffic prioritization (e.g., according to IEEE 802.1p) has the effect of providing admission control and implicit bandwidth reservation. A sending network device (the “sender”) that wants to initiate a new transmission over the network first enters a probing mode in which it sends data packets at a priority level that is lower than the target priority level and at a transmission rate up to a peak probing transmission rate that may be the same or slightly higher than the desired transmission rate. If the sender determines based on feedback regarding the probing transmission that the network can support a transmission at the peak probing transmission rate and the probing priority level, it switches to a steady mode in which it sends data packets at the desired transmission rate and at the target priority level.

Abstract: A radio module that detachably connects with a host device. A radio module is provided that includes an antenna as an integral part of the radio module. The antenna satisfies regulatory requirements by being an integral part of the radio module. The radio module includes an interface circuit that provides the processing required for communication over a wireless network. The functionality of the interface can be divided between the radio module and the host device. The physical interface between a host device and the radio module may depend on which functions are implemented by the radio module and which functions are implemented by the host device. In one example, the physical interface is a standard connection that permits the radio module to be detachably connected with multiple devices. The radio module also includes a flexible cable such that the radio module can be optimally positioned within the wireless network.

Abstract: Real-time communication of multimedia data over heterogeneous networks that may include constant delay networks, variable delay networks that have a common reckoning of time, and variable delay networks that do not have a common reckoning of time. If there are any variable delay networks in which there is no common reckoning of time in the heterogeneous networks, a common reckoning of time is established in each of those networks. Then, a constant delay network is emulated for each variable delay network using the specific common time reckoning present in each variable delay network.

Abstract: Systems and methods for verifying the authorization of a server to provide network resources to a client. At selected times, the client asserts an authorization interrupt, which will disable some or all non-essential functions of the client unless the server's authorization is verified within an allotted period of time. The client creates a client message by generating a random number and combining it with a client identifier and a value that specifies the current time. The client message is encrypted and sent to the server. Only authorized servers can decrypt the client message and create an encrypted service message that includes the random number. The service message can also contain an authorization code specifying the services that the client may receive, and an expiration count indicating when the authorization procedure will be repeated. The client receives and decrypts the service message.

Abstract: Systems and methods for compositing an image directly from multiple source image data for reducing system memory footprint and bandwidth and for improving color quality of the image. The image is divided into spans, lines, and slices. Each line includes at least one span and each slice includes at least one line. All lines in a slice have spans associated with identical sources. An image is composited by reading the image data directly from one or more sources of each span. If necessary, the sources are blended. A control structure is used to provide the image context and identifies the sources of the spans. The control structure includes headers for each data stream from each source of each span. Also, the color quality of the image is improved by reducing the number of color space conversions that occur as the image is composited. All sources in the same color space are blended before being blended with sources from other color spaces. Preferably, no more than a single color conversion is required.

Abstract: In a network of interconnected multimedia source, transfer, and sink ports, the described subject matter defers port parameter selection until substantially all relevant information is available. Specifically, parameters are negotiated between multiple ports by specifying parameter sets corresponding to the ports. Each parameter set is expressed as a list of constraints on allowable values or ranges of values. When connecting multiple ports, the constraints on their parameter sets are conjoined to form a parameter set intersection. The parameter sets of the ports are limited to values included in the parameter set intersection. Parameter sets relating to other ports are potentially limited based on the intersection results. The conjoining and limiting operations are repeated until the various parameter sets exhibit no further limitations in response to further repetitions. This process is repeated for all port interconnections.

Abstract: Systems and methods for verifying the authorization of a server to provide network resources to a client. At selected times, the client asserts an authorization interrupt, which will disable some or all non-essential functions of the client unless the server's authorization is verified within an allotted period of time. The client creates a client message by generating a random number and combining it with a client identifier and a value that specifies the current time. The client message is encrypted and sent to the server. Only authorized servers can decrypt the client message and create an encrypted service message that includes the random number. The service message can also contain an authorization code specifying the services that the client may receive, and an expiration count indicating when the authorization procedure will be repeated. The client receives and decrypts the service message.

Abstract: A graphics system includes triangle-engine for real-time rendering into a displayable frame-buffer of image data derived from vertex-based deferred instructions. The system uses homogeneity values (1/w values) for z-buffer-like occlusion mapping as well as for texture mapping. Depth resolution is enhanced for both occlusion mapping and texture mapping by representing (1/w), (u/w) and (v/w) values in a block-fixed format.

Abstract: A digital signal processing architecture is inherently cyclical in nature, by providing a timer which can be programmed to reset the processor and return to the first instruction periodically, typically once each sample of the input sample stream. Pipeline operation is enhanced through the use of a double buffering system in which operands are latched into the first stage of a double buffer as soon as they are ready, but they are transferred to the second stage only when the last-ready operand is available and the computation unit is ready to receive the operands. The computation unit receives the operands in the second stage of the buffers. The processor communicates with an external unit via a random access memory and a plurality of FIFOs. Each FIFO is associated with a respective location in the random access memory. Whenever the processor retrieves a value from one of these locations in the random access memory, control means automatically refills that location from the corresponding FIFO.