Abstract: A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that corresponds to a memory location that is transferred individually. A first value of a block identifier bit is associated with the first address, with the first value identifying the first address as an individual address. The first address and the first value of the block identifier bit are stored into the queue. A further address of the plurality of addresses is recognized as a block address corresponding to a plurality of contiguous data words that reside at a respective plurality of contiguous addresses, that begin with the further address, and that are transferred as a block unit. A second value of the block identifier bit is associated with the further address, the second value identifying the further address as a block address.

Abstract: A "bit-sliced" construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values, processor operations and invalidation operations can be "overlapped", and even operate simultaneously.