Abstract: A system and method compensate for latency, where the system includes a transmit module and a receive module that implements a DLL in a pseudo synchronous communications link. The method includes determining maximum data latency based on synchronous latencies and analog delays; measuring an actual data path latency by determining a delay in receiving a test pattern transmitted from the transmit module at the receive module using a common synchronization pulse provided the transmit and receive modules simultaneously or with a known fixed latency separation during calibration; determining a latency difference between the determined maximum data latency and the measured data path latency; and compensating for the latency difference for a subsequent data signal transmitted from the transmit module in the pseudo synchronous communications link, such that a total latency of the system with regard to the subsequent data signal is equal to the maximum data latency for the system.

Abstract: A system and method compensate for voltage and temperature variations in a pseudo synchronous communication link. The method includes receiving a data signal at a DLL through first and second variable delay circuits for performing eye tracking, keeping a sample point of the data signal in the center of a data eye having a UI; initially determining a tap size for taps of the first and second variable delay circuits; automatically selecting a number of taps of a third variable delay circuit that provides a specified delay time equal to a time value of the UI; automatically adjusting the number of taps in response to changes in the tap size; determining how many taps are equal to one half of the time value of the UI; and adjusting the number of the taps of the first and second variable delay circuits using the adjusted number of taps.

Abstract: A probe apparatus has first and second access ports and a measurement port. The first and second access ports are adapted to be interposed in a test circuit. A voltage amplifier and a voltage splitter are adapted to present the second access port and the measurement port each with a voltage representative of a voltage received by the first access port.

Abstract: Uncontrolled characteristic impedance along a spring biased pin probe assembly is avoided by providing a stepped shelf of ground plane that extends outward along the pin and toward the target signal. The length of outward extension is chosen such that even when there is only (or at least) an expected minimum amount of compression of the spring while producing and maintaining contact, the entire exposed portion of the pin is over the shelf, whose depth of step has been selected to produce a selected Z0 for the exposed pin that matches Z0 for existing transmission lines already within the probe assembly. The spring biased pin may be a resistor tip spring pin that includes a small resistor in its tip.

Abstract: An interconnect formed using a stiff layer having a plurality of holes extending there through. A first flexible layer is bonded to a first side of the stiff layer. The first flexible layer having a plurality of conductive bumps, each conductive bump being positioned over a hole. A second flexible layer is bonded to a second side of the stiff layer. The second flexible layer having a plurality of conductive bumps, each conductive bump being positioned over a hole. Signal paths are formed in the holes, the signal paths connecting the plurality of conductive bumps on the first layer to the plurality of conductive bumps on the second layer.

Abstract: A probe that connects test and measurement equipment to a device under test via a plurality of cables. The probe is formed of a plurality of printed circuit boards that are stacked together. Each board is connected to one of the plurality of cables and has a longitudinal set of pads along an edge electrically connected to the cable. The stacked plurality of printed circuit boards form a two dimensional array of pads for connecting to a similar set of pads on a device under test.

Abstract: A probe that connects test and measurement equipment to a device under test via a plurality of cables. The probe is formed of a plurality of printed circuit boards that are stacked together. Each board is connected to one of the plurality of cables and has a longitudinal set of pads along an edge electrically connected to the cable. The stacked plurality of printed circuit boards form a two dimensional array of pads for connecting to a similar set of pads on a device under test.

Abstract: An interconnect having a stiff layer, such as a PCB, having a plurality of holes therein. A first flexible layer is bonded to a first side of the stiff layer, the first flexible layer having a plurality of conductive bumps thereon positioned over holes. A second flexible layer is bonded to a second side of the stiff layer, the second flexible layer having a plurality of conductive bumps thereon positioned over holes. Vias connect the plurality of conductive bumps on the first layer to the plurality of conductive bumps on the second layer.