Abstract: A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

Abstract: A method for forming a substructure or an electrical structure. To form the substructure, a sheet of conductive material having exposed first and second surfaces is provided. A hole is formed through the sheet of conductive material. A first layer of dielectric material is applied to the exposed first surface, after the forming the hole. No material was inserted into the hole before applying the first layer of dielectric material to the exposed first surface. To form the electrical structure, a multilayered laminate that includes a plurality of substructures is formed such that a dielectric layer insulatively separates each pair of successive substructures.

Abstract: A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

Abstract: A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

Abstract: A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

Abstract: Conductive substructures of a multilayered laminate and associated methods of fabrication. The conductive substructures include a 0S1P substructure, a 0S3P substructure, and a 2S1P substructure, in accordance with the notation nSmP, wherein n and m are non-negative integers, wherein S stands for “signal plane,” and wherein P stands for “power plane.” A signal plane is characterized by its inclusion of a layer comprising conductive circuitry. A power plane is characterized by its inclusion of a continuously conductive layer. Thus, a 0S1P substructure includes 0 signal planes and 1 power plane (n=0, m=1). A 0S3P substructure includes 0 signal planes and 3 power plane (n=0, m=3) with a dielectric layer between each pair of power planes. A 2S1P substructure includes 2 signal planes and 1 power plane (n=2, m=1) with a dielectric layer between the power plane and each signal plane.

Abstract: Conductive substructures of a multilayered laminate and associated methods of fabrication. The conductive substructures include a 0S1P substructure, a 0S3P substructure, and a 2S1P substructure, in accordance with the notation nSmP, wherein n and m are non-negative integers, wherein S stands for “signal plane,” and wherein P stands for “power plane.” A signal plane is characterized by its inclusion of a layer comprising conductive circuitry. A power plane is characterized by its inclusion of a continuously conductive layer. Thus, a 0S1P substructure includes 0 signal planes and 1 power plane (n=0, m=1). A 0S3P substructure includes 0 signal planes and 3 power plane (n=0, m=3) with a dielectric layer between each pair of power planes. A 2S1P substructure includes 2 signal planes and 1 power plane (n=2, m=1) with a dielectric layer between the power plane and each signal plane.