Patents by Inventor Donald P. Richmond, III

Donald P. Richmond, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6355981
    Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: March 12, 2002
    Assignee: ChipScale, Inc.
    Inventors: John G. Richards, Donald P. Richmond, III, Wendell B. Sander
  • Patent number: 5904496
    Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: May 18, 1999
    Assignee: Chipscale, Inc.
    Inventors: John G. Richards, Donald P. Richmond, III, Wendell B. Sander