Abstract: A method of providing operational features for a programmable radio (202) employs a security key (210). The security key (210) is preferably coupled to an interface device (208) and includes at least an indication of a desired feature set. Using this indication, or flashcode (220), the programming system is able to securely program (609) the radio (202) with the desired feature set (504).

Abstract: In a system where 2-level modulation and 4-level modulation of communication signals exist, an apparatus (107) demodulates either modulation scheme by demodulating (301) a received signal under the presumption that it is a 4-level signal, and if the received signal is detected (309) to be a 2-level signal, the signal is then demodulated (319) as a 2-level signal.

Abstract: A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data stream (302) comprises a plurality of data edges (108, 110) and is sampled by a first clock signal (320). A plurality of clock edges (102, 104) defining transitions from one logic state to another is used to define "early" and "late" data edge occurrences. These occurrences are accumulated in accumulators (310, 312) and used as inputs to a clock counter (318) which produces a phase-adjusted clock signal (320). Additionally, the data transmission receiver comprises a detector (330) for detecting when a limited data stream (306) is synchronized with the phase-adjusted clock signal (320) and, in accordance with a predetermined algorithm, is able to switch the phase-lock circuit from the first bandwidth mode to the second bandwidth mode.

Abstract: An improved clock recovery enchancement circuit is provided that is particularly adapted for solving the problem caused by an incoming signal that is asymmetric and comprises a sub-harmonic tone of the bit rate clock, that is 180.degree. out of phase with the recovering clock, thereby causing the data edges to appear to be locked. The clock recovery enhancement circuit, according to the invention, provides a window signal near a predefined edge of the recovering clock which creates a disable signal such that clock adjustments may be biased towards one direction.