Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the oscillator signal generated by its own CGD unit. When the two systems are merged, one oscillator is designated as master, and its output is employed to derive the clock and definer signals on both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local oscillator signal, which is in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the clock and definer signals generated by its own CGD unit. When the two systems are merged, one CGD unit is designated as master, and its clock and definer signals drives both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local clock and definer signals, which are in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level.

Abstract: A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop, which phase offset is due to circuit delays in the phase detector. Simultaneous "pump up" and "pump down" signals, present even during apparent phase lock because of such circuit delays, are peak sampled through long lime constant filters and summed to derive a compensating signal which is applied to the reference input to the differential amplifier which controls the local oscillator, thereby exactly counteracting the offset component of the voltage appearing at the signal input to the differential amplifier which is developed during normal operation of the phase detector, filter and summing circuit of the phase locked loop at apparent phase lock.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simultaneous "pump up" and "pump down" signals, present even during apparent phase lock. A second pair of flip-flops (or a single flip-flop) of the same type used in the phase detector is sampled to obtain a compensating signal which is applied to the reference input of a differential amplifier in the loop filter. Each of the second pair of flip-flops is forced to assume a permanent state (for example, set) such that their respective Q and Q-bar outputs are always representative of the logic voltage levels at the corresponding outputs of the flip-flops in the phase detector from which the "pump up" and "pump down" are sourced.

Abstract: A circuit for signal generation and synchronization is disclosed for a ring network in which a number of stations communicate with each other. The circuit, which is provided at each station in the ring, includes a phase locked loop which loosely couples the transmit and receive clocks of each station during a repeater mode of operation. During a transmit mode the receive and transmit clocks are de-coupled so that phase delay around the ring does not degrade the transmit clock each time a transmission is initiated. The circuit includes logic gates for detecting the transmission of a token, means for generating a token and means for jam syncing the transmit and receive clocks to detect transistions in the incoming data during the repeater mode and after a token has been generated at the end of the transmit mode.