Abstract: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body by a distance d.

Abstract: A ferroelectric device that comprises a polarizing thin film of BaMF.sub.4 deposited on a substrate. Ba is barium, M is one of the metals of the group consisting of iron (FE), manganese (Mn), cobolt (Co), nickel (Ni), magnesium (Mg), and zinc (Zn). The substrate is silicon, sapphire, or gallium arsenide. A non-volatile NDRO and DRO memory cell and methods for depositing the thin film. A method of depositing bismuth titanate on a substrate are described.

Abstract: Double complementary storage is provided for a single binary digit in a quad store cross-tie memory. A correlated double sampling signal processing system is used to increase data signal level and facilitate discrimination in cross-tie memories. A method is also provided for accomplishing write and read functions in a quad store cross-tie memory using only a single pulse for either function. A set of four memory elements, arranged in two row-aligned complementary pairs, stores a single data bit, and is under four column conductors for reading data, two row conductors, and a write conductor for writing data.

Abstract: A magnetoresistive random access memory array and signal processing system which provides an improved signal to noise ratio. The basic memory complex associated with the storage of a single binary digit is a quad of memory elements or cells which are addressed in complementary fashion. The enhanced read-out signal discrimination is had by utilizing a double-correlated double-sampling differential signal processing system in which complementary data is serially passed through the same path with repeated high-speed differencing which greatly reduces nonuniformity fixed patterns as well as correlated low frequency temporal noise.

Abstract: A dynamic closed-loop circulating analog memory, preferably embodied with monolithic charge coupled devices and employing a minimum number of serial data transfers, additive refresh signal processing, and dark current subtraction for limiting crosstalk degradation of the circulated signals.

Abstract: A charge coupled device that includes an output portion having a field effect transistor disposed in the potential well channel to provide a non-destructive read-out of the analog value of a charge pocket located in the portion of such potential well channel beneath the transistor. Drain, source and channel regions of the transistor are disposed transverse to the flow of charge pockets. The conductivity of the channel is modulated as a function of the value of a charge pocket in the potential well beneath the transistor.

Abstract: The invention comprises a system for scrambling, transmitting and descrambling the video portion of a TV signal. In the preferred embodiment two serial memories (charge coupled devices) are utilized to store data representing selected portions of the video to be scrambled. The charge coupled devices are selectively clocked to interchange portions of video, with the point at which the interchange occurs determined by a code pattern generator and changing in a predetermined manner. The point of interchange is updated or changed as determined by a code pattern generator and changing every three lines of the TV signal. Descrambling is accomplished by an identical hardware arrangement with the exception that the code pattern generator at the descrambler is synchronized with the code pattern generator in the scrambler. Synchronizing information can be transmitted to the descrambler in any convenient fashion including inserting the data in an unused video line of the vertical retrace interval.

Abstract: A charge coupled device that includes an output portion having a field effect transistor disposed in the potential well channel to provide a non-destructive read-out of the analog value of a charge packet located in the portion of such potential well channel beneath the transistor. Drain, source and channel regions of the transistor are disposed transverse to the flow of charge packets. The conductivity of the channel is modulated as a function of the value of a charge packet in the potential well beneath the transistor.

Abstract: An integrated circuit sequential processor includes a charge-coupled device having input and output diffusion regions in a semiconductor substrate and a plurality of electrodes therebetween on an insulating layer formed on the semiconductor substrate. Switching means are coupled between an analog signal input and the electrodes for selectively applying a sequence of voltage potentials to the electrodes in order to meter onto the capacitor formed at the output diffusion region, charge corresponding to the sequence of voltage potentials. A circuit including a potential converting means is coupled to the output diffusion region for storing a potential indicative of the charge on the capacitor formed at the output diffusion region. The circuit also includes an output capacitor for providing an output potential indicative of the potential on the storing capacitor in response to a signal.

Abstract: A radiant energy sensor incorporating a substrate having two electrodes on a first surface and a third electrode on a second surface is described wherein a first electrode collects a first portion of charge generated by radiant energy absorbed in the substrate to provide an output signal and wherein the second electrode is biased with a voltage supply to attract and remove a second portion of charge from the substrate and first electrode to prevent blooming due to excess charge. The sensor includes a layer of semiconductor material deposited over the substrate and over the first and second electrode to conserve detector area and to permit the location of circuitry over top of the second electrode.

Abstract: A charge control circuit for bidirectionally transferring metered amounts of charge, selectively, through a transfer channel of a four gate electrode charge coupled device (CCD) is disclosed. The bidirectional charge control circuit is used primarily to increment and decrement metered amounts of charge respectively to and from a charge storage medium. More specifically, five electrical signals are generated to have varying potentials in accordance with predetermined time sequences. These signals are applied to the four gate electrode CCD in a selected one of two states to either increment or decrement a metered amount of charge therethrough to or from the charge storage medium respectively, in a predetermined number of five segments. One of the generated signals governs the metering of charge for each increment or decrement operation.

Abstract: A method and apparatus for multiplying a plurality of samples of first and second analog signals and summing the products there obtained. In stages of a first charge coupled device (CCD), charge packets corresponding to samples of the first analog signal are separated by charge packets corresponding to a first bias potential. In stages of a second CCD, charge packets corresponding to samples of the second analog signal are separated by charge packets corresponding to a second bias potential. In each step, a sum-of-products of samples and bias potentials is obtained.

Abstract: An analog multiplier for multiplying the signals derived from a charge coupled device (CCD) tap includes a balanced multiplier of a first conductivity-type and a buffer of a second conductivity-type coupled between the CCD tap and the balanced multiplier. The multiplier includes first and second transistors, the drains of which are coupled together to form an input. The buffer includes a load transistor coupled to the output of an amplifying transistor. Means are included for coupling the output of the amplifier transistor and the multiplier input.

Abstract: A stabilized charge injector for charge coupled devices (CCD) includes a diffusion and two or more gate structures in a CCD channel wherein the diffusion alternately acts as a source and drain of the minority-type signal carriers. D.C. signals are applied to the gates immediately adjacent the diffusion and the next successive adjacent gate to provide a charge injection which is proportional to the difference between the signal voltage applied to the one of the two gates and a DC reference voltage applied to the other thereof. Low noise performance is achieved through utilization of a quasi-static operation in which neither of the aforementioned gates adjacent the diffusion is pulsed. Moreover, the use of a gate injector presents at the input, a true capacitance defined as a function of the gate oxide layer. Hence, the value of capacitance is constant and independent of the signal voltage applied.

Abstract: In a charge transfer device (CTD), such as a charge coupled device (CCD), a gate electrode employed for sensing of the charge packet being transferred, or coupled through the device is clocked during one phase of the four-phase clocking and is permitted to float, i.e., be isolated, during a sensing phase of the four-phase clocking. Since the sensor is a gate electrode rather than a diffusion, it presents no obstruction to the propagation of charge down the channel. Since sensing occurs while the electrode is floating, the sensing or readout function does not have any detrimental effect on the propagation of charge down the channel, i.e., it affords a truly non-destructive readout. During a clocking phase in which charge is isolated under a different gate electrode, an attractive voltage clock pulse is applied to the sensor electrode, rendering it attractive.

Abstract: Extended correlated double sampling (ECDS) for charge transfer devices (CTD) corrects for errors arising in components of the CTD system from the input to the output thereof. Sources of error include bias variations and non-uniformity of thresholds and leakage currents. While applicable to any type of CTD system, for a TDI (time delay integration) application, precise error correction is achieved. Alternate signal level samples and reference level samples, the latter preferably AC zero, are propagated down the CTD channel as a related pair. At the CTD output, the signal and reference level samples of each pair are differenced, thereby correcting the resultant output signal for the noted types of errors. ECDS is compatible with CDS as taught in U.S. Pat. No. 3,781,574 and the two may be used jointly.

Abstract: A programmable analog transversal filter is disclosed for processing analog signals and comprising a charge-coupled device (CCD) for receiving a series of discrete analog signals to be delayed by increasing periods and applied to the outputs of the CCD, and a plurality of MNOS memory devices coupled to the taps of the CCD and programmed so that the output of a CCD tap is multiplied by a particular factor. In turn, the outputs of the MNOS memory devices are summed to provide an output signal ##EQU1## where W.sub.k is the weighting factor associated the k.sup.th MNOS memory device. The weighting factors are set into the system by varying the threshold voltage of the corresponding MNOS device.