Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract: An integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein the at least one memory state backup circuit includes at least one passive variable resistance memory cell and at least one passive variable resistance memory cell interface that are used to backup data from the active memory circuit to the PVRM cell. Data is then placed back into the active memory circuit from the PVRM cell during a restore operation. The PVRM cell interface is operative to read the PVRM cell in response to a restore signal. PVRM cell interface control logic is operative to remove power to the PVRM cell after backup of the data to the PVRM cell from the active memory circuit. A PVRM cell (e.g., a bit cell) is added to each memory circuit that stores state information on an integrated circuit.

Abstract: An integrated circuit employs a plurality of functional blocks, such as but not limited to, processors (e.g., cores), and an on-die distributed programmable passive variable resistance memory array configured to provide configuration information for each of the plurality of functional blocks. A corresponding sub-portion of the on-die distributed programmable passive variable resistance memory array is fabricated in layers above each respective plurality of functional blocks. The on-die distributed programmable passive variable resistance memory array is used as either non-volatile prepackage configuration information store, or a non-volatile post-package configuration information store that may allow dynamic changing of hardware configuration of the functional blocks both during normal operation and prior to die packaging. A method for making the same is also disclosed.

Abstract: A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

Abstract: A memory system is provided, including a first memory comprising a plurality of bitcells configured to store data, and a second memory, configured to store an index of the data stored at a corresponding location in the first memory and further configured to store repair information, wherein the repair information indicates a bitcell error at the corresponding location in the first memory.

Abstract: Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

Abstract: Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

Abstract: Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

Abstract: A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

Abstract: A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

Abstract: According to one embodiment, a method comprises detecting a defect in a portion of memory. The method further comprises designating the portion of memory as defective, and avoiding attempts to access the portion of memory designated as defective.

Abstract: A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.

Abstract: The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable weak write test mode (PWWTM) bias generator includes an output signal that is a logic high in a default mode when a WWTM is not active. When the WWTM is active, the generator output signal is the bias voltage having the selectable magnitude. The default mode logic high is actively maintained when the generator output is connected to a load, such as the write driver of the SRAM array. A WWTM-enabled SRAM system includes the PWWTM bias generator. A method of driving a WWTM-equipped SRAM includes generating and applying the output signal to a gate of a weak write pull-down transistor of the SRAM array write driver in the default mode and the WWTM.

Abstract: According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

Abstract: The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable weak write test mode (PWWTM) bias generator includes an output signal that is a logic high in a default mode when a WWTM is not active. When the WWTM is active, the generator output signal is the bias voltage having the selectable magnitude. The default mode logic high is actively maintained when the generator output is connected to a load, such as the write driver of the SRAM array. A WWTM-enabled SRAM system includes the PWWTM bias generator. A method of driving a WWTM-equipped SRAM includes generating and applying the output signal to a gate of a weak write pull-down transistor of the SRAM array write driver in the default mode and the WWTM.

Abstract: The present invention uses metal programming to facilitate modifying a range and/or resolution of a bias voltage output signal generated by a programmable bias generator. A metal-programmable (MP) bias generator includes a MP transistor in the bias generator. The MP transistor includes either or both of a MP pull-up transistor and a MP pull-down transistor, each having a respective ON state resistance. A method of modifying the bias generator includes metal programming either or both of the MP pull-up transistor and the MP pull-down transistor, such that the respective ON state resistance of the corresponding metal-programmed transistor is combined with an effective ON state resistance of circuitry of the bias generator. The combined ON state resistances change one or both of the range and the resolution of a set of available magnitudes of the bias voltage output signal.

Abstract: An embodiment of the invention provides a circuit and method for reducing silent data corruption in storage arrays with no increase in read and write access times. An N bit parity encoder is connected to an N bit storage array. When the N bit array is written, the data used to write into the storage array is also used to generate a parity value by the N bit parity encoder. This parity value is stored in a latch. When the N bit array is read, the current parity value of the parity encoder is presented to the state machine. The state machine compares the current value of the parity encoder to the stored value in the latch. If the parity values, stored and observed, don't match, the state machine indicates that data corruption may have occurred.

Abstract: A system and method are disclosed which provide a built-in self test (BIST) for a content addressable memory (CAM) structure. In a preferred embodiment, an integrated circuit (chip) comprises a CAM structure that is accessible by a processor to satisfy memory access requests and a BIST implemented within such chip, which enables testing the integrity of the CAM structure. Such a preferred embodiment comprises a BIST that enables testing the integrity of the CAM structure that does not require circuitry for reading memory data out of the CAM structure. A preferred embodiment can also be utilized for testing a random access memory structure. In a preferred embodiment, a CAM BIST comprises logic capable of generating test values (e.g., a test pattern), a shift register that temporarily stores the test values generated by the logic, and compare circuitry that determines whether a test value matches an entry within the CAM structure.