Abstract: In combination with a transistor designed to drive an inductive load, there is included a network connected between the output electrode (e.g., drain) and the control electrode (e.g., gate) of the transistor for limiting the overshoot and controlling the waveshape of the signal produced at the output electrode of the transistor, when the transistor is being turned-off. The network includes a series string of zener diodes with one or more by-pass capacitors connected across the zener diodes closest to the control electrode of the transistor for shaping the output signal produced at the output electrode of the transistor and for reducing electromagnetic radiation. The network also includes unidirectional conducting elements for discharging each bypass capacitor each time the transistor is turned-on. The zener diodes and the "discharging" unidirectional conducting elements of the network may be formed as integral parts of the same integrated circuit (IC).

Abstract: A network is connected between the drain and gate of a transistor for limiting the overshoot and controlling the waveshape of the signal produced at the drain of the transistor, when the transistor is being turned-off. The network includes a series string of zener diodes with one or more by-pass capacitors connected across one or more zener diodes for shaping the output signal produced at the drain of the transistor and for reducing electromagnetic radiation. The network also includes unidirectional conducting elements for discharging each bypass capacitor each time the transistor is turned-on. The zener diodes and the "discharging" unidirectional conducting elements of the network may be formed as integral parts of the same integrated circuit (IC). For best results, the bypass capacitors are connected across the zener diodes closest to the gate of the transistor.

Abstract: An EPROM cell comprises an MOS device including a floating gate electrode overlying, and ohmically insulated from, the channel region of the MOS device, and a separate diode including a p-n junction having a substrate surface intercept. A floating gate electrode overlies the diode p-n junction intercept and is ohmically isolated therefrom by an intervening insulating layer. Writing of data into the floating gate electrode of the MOS device is achieved by causing a voltage breakdown across the diode p-n junction and the flow of high energy electrons across the junction. A voltage is simultaneously applied to the diode gate electrode thereby attracting some of the high energy electrons through the overlying insulating layer into the diode floating gate electrode. The diode gate electrode is ohmically connected to the MOS floating gate electrode on which some of the electrons are stored for affecting the turn-on, turn-off characteristics of the MOS device.

Abstract: A network for preventing large transient currents in the conduction paths of a pull-up transistor connected between a first point of operating potential and an output point and a pull-down transistor connected between the output point and a second point of operating potential. The network includes a third transistor having its base to emitter path connected in parallel with the base to emitter path of the pull-down transistor and its collector coupled to the base of the pull-up transistor. The collector current of the third transistor is limited, causing it to saturate at a given current level and to then limit the flow of additional base drive to the pull-down transistor, whereby the maximum collector current of the pull-down transistor is also limited. In addition, a diode is connected between the output point and the collector of the third transistor.