Abstract: A buffer circuit is disclosed as part of a centralized subsystem in a telephone switching system. The subsystem performs all functions heretofore performed by individual originating registers and communicates with office pretranslators for effecting digit pretranslation. The buffer circuit interfaces a computer of the subsystem with a conventional pretranslator connector for obtaining access to the office pretranslators preferentially over originating registers which are competing for the pretranslators. In response to a single call, the buffer applies a bid for service to each of a plurality of pretranslator connector subgroups in contrast with a bid to a single subgroup from each originating register. In the event the computer receives overlapping calls, the buffer circuit holds the multiple bids for service to preserve their priority status in the queues of the connector subgroups.

Abstract: A stored program digital signal processor (e.g., Digital Equipment Corporation PDP 11/40) is used to collect billing data (e.g., Initial Entry data for Automatic Message Accounting) from a common control circuit (e.g., marker) of a common control automatic telephone switching system (e.g., the Bell System No. 5 Crossbar system). Ten marker control status indicating leads are scanned by the signal processor fast enough to detect any change in the signals on the 10 status leads which, in signal content as a group, represent the control status of the marker at any given time. When two successive prescribed control status changes occur, a large number of marker data leads are scanned by the signal processor so as to allow collection of that data and the storage thereof in a marker core buffer area of the signal processor.