Abstract: Software is tested for execution on data processing apparatus with plural processors that share access to a memory. The memory has a memory ordering type specifying an ordering freedom which allows memory access requests to be processed out of order from an original program order. A simulator for each processor executes a sequence of instructions in program order. An access buffer associated with one of the processor simulators receives and stores access requests issued by that simulator when executing access instructions within the sequences. A controller selects and applies an eviction policy to determine an order in which access requests are output from the access buffer to the memory so that the ordering freedom is exercised in a manner compliant with the memory ordering type but to a degree exceeding that expected within the data processing apparatus.