Abstract: A packaging platform for interconnecting integrated circuit chips and cards, in which the platform is a circuitized fluoropolymer-based laminate carrier including high purity fluoropolymer protective barriers on its surfaces.

Abstract: A method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.

Abstract: Deterioration and damage to insulator materials in an interconnection structure having vertical connections due to exposure to heat during bonding of lamina is avoided by performing diffusion bonding of metal pads at plated through holes (PTH) at temperatures below the melting points of conductive material in the bond. Diffusion bonding is achieved during time periods required for processing (e.g. curing or drying) of insulating materials in the laminated structure.

Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.

Abstract: A method of making a circuitized substrate such as a printed circuit board having at least one hole therein which comprises the steps of providing a layer of dielectric, forming at least one (and preferably several) holes therein, providing a fill member including a quantity of fill material and reinforcement means located within the fill material, positioning the fill member on the dielectric over the holes and thereafter applying a predetermined force sufficient to cause only the fill material to be forcibly driven into the accommodating hole(s), not the reinforcement means. Subsequent steps can include forming a layer of circuitry on the substrate's external surface and over the filled holes such that an electrical component such as a ball grid array (BGA), semiconductor chip, etc. may be directly positioned on and/or over the hole(s). A fill member usable with the method is also provided.

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract: The present invention provides a method of filling an at least one aperture in a semiconductor substrate by placing a sacrificial carrier structure on a surface of the substrate, wherein the structure comprises, a first layer, a fill material over the first layer, and a mask over the fill material having at least one opening therein, such that the opening at least partially aligns with the aperture in the substrate. Thereafter, the fill material is forced into the aperture by the application of heat and pressure, and the sacrificial carrier structure is removed.

Abstract: An electronic interconnection assembly having a thin film bonded to either a glass ceramic or to an organic laminate substrate, and a method for attaching a thin film wiring package to the substrate. Provided is the utilization of adhesives which may be processed at significantly lower temperatures so as to avoid damaging components, the wiring package and interconnection joints. Moreover, pursuant to specific aspects, the joining of the thin film to the substrate may be implemented with the utilization of dendrites.

Abstract: A process of removing holefill residue from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.

Abstract: Deterioration and damage to insulator materials in an interconnection structure having vertical connections due to exposure to heat during bonding of lamina is avoided by performing diffusion bonding of metal pads at plated through holes (PTH) at temperatures below the melting points of conductive material in the bond. Diffusion bonding is achieved during time periods required for processing (e.g. curing or drying) of insulating materials in the laminated structure.

Abstract: A composition usable in hole filling of a metal layer and to planarize the metal layer is provided. The metal layer is part of a substrate which can be part of a multilayer printed circuit board or chip carrier. The composition comprises a fluoropolymer dielectric metal, a filler material, and a coupling agent, the filler material having at least a partial coating of the coupling agent thereon.

Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.

Abstract: A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.

Abstract: The present invention relates to a method and structure for providing an interconnect between layers of a multilayer circuit board.

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract: The present invention relates to a structure for providing an interconnect between layers of a multilayer circuit board. The structure comprises a stack that includes at least one layer and a via opening that extends through at least one layer of the stack. Each individual via opening is filled with a solid conductive plug and each solid conductive plug has a first contact pad and a second contact pad.

Abstract: Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with heat spreading perforated cap wherein the perforations are filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, resulting in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A platen for use in a laminating press is provided which includes a body of material having first and second faces and spaced first and second ends. Preferably, at least one heating device is disposed in the body of material. First and second spaced cooling channels are formed in the body of material, the first cooling channel being adjacent the first face and having a fluid inlet port adjacent to or in the first end, and a fluid outlet port adjacent to or in the second end, and a second cooling channel being adjacent the second face and having a fluid inlet port adjacent to or in said second end, and a fluid outlet port adjacent to or in the first end. The invention also contemplates using such platens for laminating a book or stack of sheets of material to form a unitary single member having reduced stresses.

Abstract: A composition usable in hole filling of a metal layer and to planarize the metal layer is provided. The metal layer is part of a substrate which can be part of a multilayer printed circuit board or chip carrier. The composition comprises a fluoropolymer dielectric metal, a filler material, and a coupling agent, the filler material having at least a partial coating of the coupling agent thereon.