Patents by Inventor Donald Stephen Bitting

Donald Stephen Bitting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8259454
    Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; at least one electronic device having a first surface and a second surface, wherein the electronic device is secured to the base insulative layer; at least one I/O contact located on the first surface of the electronic device; and a frame panel defining an aperture, wherein the electronic device is disposed within the aperture, and the frame panel is a multi-functional structure having a first region comprising a first material, wherein a surface of the first region secures to the base insulative layer; and a second region comprising a second material, wherein the first material and the second material differ from each other and have differing adhesability to the base insulative layer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: September 4, 2012
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Donald Stephen Bitting, Daniel Lee Abraham
  • Patent number: 7777333
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Publication number: 20090255709
    Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; at least one electronic device having a first surface and a second surface, wherein the electronic device is secured to the base insulative layer; at least one I/O contact located on the first surface of the electronic device; and a frame panel defining an aperture, wherein the electronic device is disposed within the aperture, and the frame panel is a multi-functional structure having a first region comprising a first material, wherein a surface of the first region secures to the base insulative layer; and a second region comprising a second material, wherein the first material and the second material differ from each other and have differing adhesability to the base insulative layer.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 15, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Raymond Albert Fillion, Donald Stephen Bitting, Daniel Lee Abraham
  • Publication number: 20090072393
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Application
    Filed: February 24, 2006
    Publication date: March 19, 2009
    Applicant: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Patent number: 5955381
    Abstract: The quartz shadow ring of a conventional plasma etching apparatus is desirably coated with material which inhibits the liberation of oxygen into the plasma. Investigation has shown that the liberated oxygen degrades etching uniformity across the wafer.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: September 21, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Donald Stephen Bitting, Thomas Craig Esry, David Huibregtse, Paul Edward Wheeler