Abstract: An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.

Abstract: An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

Abstract: An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

Abstract: An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

Abstract: An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.

Abstract: An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

Abstract: A method and system for transmitting and receiving high-frequency electrical communication signals over a previously installed building power line network is presented, in which minimal or no electrical modifications of the power line network are required. A high-frequency signal is impressed between earth ground/neutral and building ground power lines that are tied into a common ground bar at a service panel. The high-frequency signal isolates the earth ground line/neutral and building ground lines by creating an “anti-resonant” condition. Since building ground is required by electrical safety codes to be present at all electrical outlets within the building, the carrier signals can be transmitted and received from any electrical outlet within the building.

Abstract: A closed loop control system for controlling the temperature of a heated substrate is presented. In the preferred embodiment, the closed loop control system is implemented substantially or completely on a single substrate. The closed loop control system comprises means to reduce or eliminate parasitic feedback in the control system. In one aspect of the present invention, the mechanism for reducing the effects of parasitic feedback comprises a mechanism to prevent minority carriers from collecting around the base of the temperature sensing device. The mechanism for preventing minority carriers from collecting around the base of the temperature sensing device can be one or more guard rings which attract the minority carriers and prevent them from collecting around the base of the temperature sensor.

Abstract: An electrical circuit for generating a polynomial function in response to a linear input signal is disclosed. The circuit in one embodiment comprises a primary and a secondary current mirror, with the collector or source of the secondary current mirror connected in common with the input signal of the primary current mirror. The output signal of the electrical circuit is taken at the mirrored current source terminal of the first current mirror. The primary and secondary current mirrors are biased to at least initially respond exponentially to the linear input signal. Each then transitions into the more linear, resistor-dominated range. The primary current mirror is enabled at a predetermined cut-in level, such that an upward curving exponential response function is generated in response thereto.

Abstract: A novel compensation device for conditioning or generating signals to have an arbitrarily defined shape, produced to an arbitrarily specified accuracy. The device comprises a plurality of bounded polynomial function generators having outputs summed into a summing network to produce a signal which is the composite of the effects of all of the polynomial generators. Accuracy is achieved through the use of fusible link trimming of the compensation circuits, which are configured to provide mathematically well-behaved polynomial functions with predictable responses to the programming, and which produce effects only over desired segments of the range of interest. The result is a monotonic signal with no discontinuities, which can be made arbitrarily close to a specified signal.

Abstract: An improved circuit, and an improved device geometry for trimming element values in an integrated circuit employs selectable short-circuiting of fusible elements by means of application of a prescribed sequence of electrical waveforms of prescribed amplitude and polarity. The improved trim circuit configuration offers the possibility of improved trim circuit density by allowing selection of three trim elements from a single contact pad, in conjunction with a common contact pad, for each trim circuit. Replication of the circuits allows extension of the range of adjustment or of the resolution of the trim, at the expense of only one additional pad per each additional trim circuit. A unique device geometry is described for implementing the improved trim circuit within a single isolation pocket of an integrated circuit.

Abstract: A simplified temperature stabilized circuit provides a current which is proportional to a variable voltage by the use of branching transistor circuitry which fixes the voltage level of the supplied current, and controls its magnitude. The variable voltage is supplied through a reference resistor to the emitter of a first junction transistor having its base connected to the base of an identical junction transistor having its emitter grounded, thereby fixing the input voltage to the first transistor at a virtual ground potential. A third identical transistor has its base and emitter connected in parallel with the first transistor and carries an equal amount of current. Current derived in parallel from the first and second transistor is positively proportioned relative to the current flowing in the collector path of the third transistor by a pair of mirror-connected transistors having suitable relative areas and load resistors.

Abstract: The outputs of individual stages in a digital to analog converter are each trimmed by independent circuitry which includes a plurality of transistors connected to a common output terminal, the physical dimensions of each transistor being scaled in proportion to desired levels of current flow, and selectable switches connected in circuit with each of the transistors. Selectable switches are actuable to produce an output trimming current of a desired magnitude, which current is used to correct the untrimmed stage output. The invention includes circuitry for controlling the polarity of the trimming current relative to the stage, and for selectively expanding or contracting the trimming range to optimize the trimming currents for the particular characteristics of the converter. A favorable balance between trimming accuracy and the area occupied by the trimming circuitry is attained by the use of both emitter-scaled and multicollector transistors in the trimming circuits.

Abstract: Novel apparatus is described for controlling the application of circuit adjustment signals to an electrical circuit device. The same device leads are used in an operating mode with input signals in a first range, and in an adjustment mode with input signals in a second range, the two ranges being mutually exclusive.An exemplary embodiment is directed toward trimming a digital to analog converter. A plurality of trimming elements are provided with an equal number of two-terminal actuating devices, which are arranged in a matrix such that each pair of terminals is connected in circuit with a unique pair of input leads. The devices actuate their associated trimming elements in response to the application of actuating signals, exceeding a threshold level greater than the level of the binary input signals, to their respective lead pairs. The leads are thereby capable of a dual mode operation, with one mode for normal converter operation and the other mode for setting up desired trim circuits.

Abstract: A digital to analog converter with bit circuits arranged in binary order, in which a supplemental current circuit is added to selected bit circuits to enable convenient and efficient conversion from binary to BCD operation. Supplemental BCD currents are controlled by a bias circuit which automatically increases the BCD bit circuit bias to a level at which the full-scale BCD output current is substantially equal to the full-scale binary output current.

Abstract: A circuit for interfacing a digital to analog converter with input signals from three different logic systems, whereby appropriate threshold switching signals compatible with each logic system are presented to the converter when the proper logic control signal is applied to the circuit. The first logic system is characterized by logic control signals within a first voltage range, and switching thresholds which differ from the logic control signals by a fixed increment; the second system by logic control signals within a second voltage range higher than the first range, and switching thresholds equal to a fixed proportion of the logic control signal; and the third system by a substantially constant switching threshold for a predetermined positive supply voltage level.