Abstract: Systems and methods are disclosed to control a buck converter with a first switching circuit including a first upper power transistor coupled to a first lower power transistor at a first junction; a second upper power transistor coupled to a second lower power transistor at a second junction; an inductor coupled to the first and second junctions; and a load coupled to the second junction.

Abstract: Systems and methods are disclosed to control a buck converter by performing adaptive digital pulse width modulation (ADPWM) with a plurality of upper power transistors each uniquely controlled to enable greater than 100% duty cycle for the buck converter and a lower power transistor coupled to the plurality of upper power transistors; and driving an inductor having one end coupled to the lower power transistor and the upper power transistors.

Abstract: A disk drive assembly includes a disk drive, one or more accelerometers, a control circuit, and an adaptive feed forward circuit. The one or more accelerometers generate acceleration signals that are used to detect rotational vibration (RV) events on the disk drive. The control circuit is configured to: generate one or more control signals, which are based on a control signal from a host system and a compensation signal from the adaptive feed forward circuit, and generate a position error signal (PES) that indicates an error in a position of a disk drive head relative to a center of a track. The adaptive feed forward circuit generates the compensation signal, which compensates for the detected RV events based on the acceleration signals and the PES. The compensation signal accounts for self-induced RV events generated by a SEEK operation that repositions the head to a new track, wherein feed forward adaption is not disturbed by the SEEK operation.

Abstract: A current sense amplifier circuit for detecting a first current includes an input gain stage incorporating a feedback loop, a current mirror, a charge integration stage and a comparator. The first current is coupled to an input node of the input gain stage where the input gain stage operates to maintain the voltage at the input node at a substantially constant level. The current mirror is coupled to mirror the first current into a second current. The charge integration stage is coupled to integrate charge associated with the second current to develop a first voltage. The comparator is coupled to compare the first voltage to a reference level and providing an output signal. The comparator generates an output signal having a first value when the first current exceeds a predetermined threshold level and a second value when the first current is less than the predetermined threshold level.

Abstract: Circuits and techniques are described for compensating for a first parasitic current corresponding to a first parasitic capacitance associated with a first switch. A second switch is configured substantially the same as the first switch, the second switch having a second parasitic capacitance associated therewith. A current mirror coupled to the second switch generates a compensating current in response to a second parasitic current corresponding to the second parasitic capacitance. The compensating current compensates for at least a portion of the first parasitic current.

Abstract: Circuits and techniques are described for compensating for a first parasitic current corresponding to a first parasitic capacitance associated with a first switch. A second switch is configured substantially the same as the first switch, the second switch having a second parasitic capacitance associated therewith. A current mirror coupled to the second switch generates a compensating current in response to a second parasitic current corresponding to the second parasitic capacitance. The compensating current compensates for at least a portion of the first parasitic current.

Abstract: A quick recovery AC coupling circuit has a coupling capacitor stage that generates an output DC-biased AC signal by capacitively coupling an input DC-biased AC signal generated by a source stage. The output DC-biased AC signal is biased by a biasing stage. The quick recovery AC coupling circuit utilizes an emitter follower which is biased at its emitter by an active device in both the source stage and the biasing stage to maintain the bias voltage across the coupling capacitor stage when the quick recovery AC coupling circuit is powered off and when a high-input impedance device is connected to receive the output DC-biased AC signal.

Abstract: A peak detector circuit operates to charge a capacitor to a level proportional to the peak input signal level. The charging circuit includes an emitter follower driver. The response time of the charging circuit is enhanced by coupling a constant current to the emitter follower output. The constant current acts to lower the emitter follower source impedance which operates to increase the rate of capacitor charging.

Abstract: A dual input differential signal summer combines a pair of differential input signals logarithmically to produce a differential output. The input signals are applied to a pair of differential amplifiers the outputs of which are buffered so that they do not interact. The result is an increased circuit transconductance. Where the circuit is employed in a tunable filter integrated circuit employing plural cascaded filter elements, a substantial reduction in chip power is achieved.

Abstract: A novel self-timing qualification channel structure is taught, suitable for use in detecting data from a magnetic disk or other storage medium. A timing comparator is used in addition to a hysteresis comparator in order to detect when the true peak of the input signal is about to occur. The timing comparator output determines when signal qualification by the hysteresis comparator is to occur. The timing comparator only allows signal qualification to occur just prior to the true peak in the input signal. Because of this, the risk of falsely detecting off track noise or noise in the shoulder region is greatly reduced. In one embodiment, the timing comparator operates without the need for additional external components by utilizing the existing channel filter. Thus, the channel filter serves two purposes: to filter the channel input signal prior to detection and to provide delay for the timing comparator.

Abstract: A low noise oscillator is described suitable for use in an AM stereo radio receiver. The oscillator circuit includes means for controlling its amplitude at a constant low level. The oscillator is amenable to electronic tuning and IC construction.

Abstract: Disclosed is a stop detector circuit for issuing a stop signal in an electronically tuned AM radio when the radio is center tuned on a radio signal that exceeds a predetermined level of signal strength. An intermediate frequency signal and an automatic gain control signal are used to determine when the stop signal is to be issued. Included in the stop detector circuit are a resonator driver (16), a resonator circuit (18), a resonator signal amplifier (20), a current switch (22), a threshold adjustment and filter (24), and a threshold detector (26). The resonator driver generates a resonator signal having a series of current pulses at the same frequency as the intermediate frequency signal. The resonator circuit converts the resonator signal current to a voltage, the AC component of which is at a minimum when the radio is not center tuned and at a maximum when the radio is center tuned. The resonator signal amplifier amplifies the resonator signal voltage.

Abstract: A radio receiver incorporates an AGC system having an upper wide band threshold and a narrow band threshold. Both thresholds are made temperature independent. The narrow band threshold is related to the circuit response to tuning meter voltage and the wide band threshold is related to the tuner output prior to i-f selectivity. When these responses are logically anded, an AGC response having the desirable characteristics of both narrow band and wide band systems is achieved. An IC form of AGC circuit is disclosed.