Abstract: A resilient sensor system is disclosed for use on a device requiring sensor data. The system includes a calibrated and an uncalibrated sensor arranged to sense the same environmental stimulus. During enrollment, the raw sensor output from both sensors is differenced over a range of sensor input to build an unclonable fingerprint of the sensor pair. This fingerprint is checked against a contemporaneously generated fingerprint to ensure continued fidelity of the calibrated sensor.

Abstract: Systems and methods for the generation and use of session keys supporting secure communications between a client and server device are disclosed. The client hashes each of a series of passwords a first number of times. The hashed passwords are sent to a server. The server applies the hashed password to an array of PUF devices, and receives an initial response bitstream which is stored. The client later hashes each of the series of passwords a second number of times, which is less than the first number, and these are sent to the server. The server continues to hash the second message digest, generate PUF responses, and compare the result to the initially stored responses. For each password, the number of hashes necessary to achieve a match is a partial session key. Latency is improved by an array of separately addressable PUFs, each producing a partial session key.

Abstract: Systems and methods for the generation and use of session keys supporting secure communications between a client and server device are disclosed. The client device has or receives a password, which it hashes a predetermined first number of times. The hashed password is sent as a message digest to a server. The server applies the hashed password to a an array of PUF devices, and receives a response bitstream which is stored. The client later hashes the password a second predetermined number of times, which is less than the first predetermined number, and this second message digest is sent to the server. The server continues to hash the second message digest, generate PUF responses, and compare the result to the initially stored responses. The number of hashes necessary to achieve a match is the session key.

Abstract: A low-power, controllable, and reconfigurable method to control weights in model neurons in an Artificial Neural Network is disclosed. Memristors are utilized as adjustable synapses, where the memristor resistance reflects the synapse weight. The injection of extremely small electric currents (a few nanoamperes) in each cell forces the resistance to drop abruptly by several orders of magnitudes due to the formation of a conductive path between the two electrodes. These conductive paths dissolve as soon as the current injection stops, and the cells return to their initial state. A repeated injection of currents into the same cell results in an almost identical effect in resistance drop. Different, stable resistance values in each cell can be controllably achieved by injecting different current values.

Abstract: A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.

Abstract: A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: An Artificial Neural Network (ANN) is a computational model that is inspired by the way biological neural networks in the human brain process information. The basic computational element (model neuron) is often called a node or unit. It receives input from some other units and/or from external sources. Each input has an associated weight (w), which can be modified so as to model synaptic learning. The present invention disclosures a low-power, controllable, and reconfigurable method to control weights in models neurons. The injection of extremely small electric currents (a few nanoamperes) in each cell forces the resistance to drop abruptly by several orders of magnitudes due to the formation of a conductive path between the two electrodes. These conductive paths dissolve as soon as the current injection stops, and the cells return to their initial state. A repeated injection of currents into the same cell results in an almost identical effect in resistance drop.

Abstract: A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.

Abstract: An apparatus and method for computer network security based on Free-Space Optical Interconnections (FSOI) for board-to-board information transmission. The addition of a controllable, interlocked shutter system creates air-gapped isolation of the boards, allowing for increased obfuscation, and enhanced security.

Abstract: An apparatus and method for computer network security based on Free-Space Optical Interconnections (FSOI) for board-to-board information transmission. The addition of a controllable, interlocked shutter system creates air-gapped isolation of the boards, allowing for increased obfuscation, and enhanced security.