Abstract: A multi-channel analog to digital conversion circuit and methods thereon are provided. The multi-channel analog to digital conversion cirucit comprises a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter wherein analog residue is processed by subsequent analog to digital converter stages. Each stage of respective linearized channels is configured for calculating gain and offset for each stage in the channel and such gain and offset is used in subsequent integration periods.

Abstract: In one aspect, the present invention provides a method for amplifying a signal including generating an input signal and amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.

Abstract: In one aspect, the present invention provides a method for amplifying a signal including generating an input signal and amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.

Abstract: A detector device used in an imaging system includes a photodiode array that is positioned to detect radiation transmitted by the imaging system. A switch array is connected to the photodiode array. The switch array has an output and comprises switch banks having switches. A control logic circuit is connected to the switch array and controls the state of the switches in the switch banks based on a predefined switching configuration. The control logic circuit also includes a memory device programmed to store the predefined switching configurations. The predefined switching configurations represent respective operational modes of the imaging system wherein each respective operational mode has a respective predetermined detector slice thickness.

Abstract: In one aspect, the present invention provides a method for amplifying a signal including generating an input signal and amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.

Abstract: The present invention provides a system for recording a viewer's television viewership habits. Sensors monitor the audio signal, synchronization signal, and video signal emanating from the television. A time coincidence channel tag is mixed with the transmitted television audio or video signal at a dwelling by a master unit. Then by matching the channel tag of the viewed channel with the channel tag, an accurate identification of the viewed channel can be made.

Abstract: A detector device used in an imaging system includes a photodiode array that is positioned to detect radiation transmitted by the imaging system. A switch array is connected to the photodiode array. The switch array has an output and comprises switch banks having switches. A control logic circuit is connected to the switch array and controls the state of the switches in the switch banks based on a predefined switching configuration. The control logic circuit also includes a memory device programmed to store the predefined switching configurations. The predefined switching configurations represent respective operational modes of the imaging system wherein each respective operational mode has a respective predetermined detector slice thickness.

Abstract: A receiver for enabling one-way communications in a GHM network which does not interfere with or reduce the capability of the GHM network. The receiver detects a small modulation factor signal present on the GHM signal normally transmitted by the GHM transmitter. If the frequency of the modulated signal corresponds to a pre-defined frequency, then the receiver generates a command signal to, for example, a relay, annunciator, or other external device. More particularly, and in one embodiment, the receiver includes a filter which partially isolates the GHM energy from the lower 60 Hz harmonics. The receiver also includes a envelope detector coupled to filter. The envelope detector is coupled to a frequency detector. The frequency detector is coupled to a command decoder. The command decoder determines whether a plurality of AM modulation frequencies are present on the received signal.

Abstract: An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits includes an operational amplifier and an integrating capacitor for storing a charge proportional to the integral of the input signal. A charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge level is removed from the integrating capacitor a number of times. The removal of the first predetermined charge from the integrating capacitor allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor.

Abstract: The present invention provides a method and apparatus which uses data containing non-linearity information regarding the integrator circuits used in over-sampled Analog-to-Digital Converters to predict the Signal-to-Distortion Ratio and the Signal-to-Noise Ratio. Input response data used to evaluate the device is either obtained from simulations when designing the integrator circuit, or in situ testing of the integrators when testing an over-sampled Analog-to-Digital Converter integrated circuit. The non-linearity data can be generated by simulating or testing the Analog-to-Digital Converter circuit for several hundred clock cycles and measuring the inputs and outputs of each integrator. This data is used to predict the Signal-to-Distortion Ratio and the Signal-to-Noise Ratio.

Abstract: The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a “steady-state” condition. After the input signal achieves a “steady-state” condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.

Abstract: The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a "steady-state" condition. After the input signal achieves a "steady-state" condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.

Abstract: A programmable clock circuit generates a plurality of phase clock signals in correspondence with an associated control word programmed into a memory. Programmable clock circuit is implemented digitally in an application specific integrated circuit. Each phase clock signal is synchronized by a master clock signal which reduces signal jitter and improves phase signal accuracy.

Abstract: A delta sigma modulator having reduced quiescent power consumption as compared to known delta sigma modulators utilizes no operational amplifiers and includes, in one embodiment, an input CCD and a summing CCD coupled to the output of the input CCD. A readout is connected to receive output signals from the summing CCD. Both an integration/recirculation input CCD and a comparator are provided to receive output signals from the readout. The integration/recirculation input CCD feeds back a charge to the summing CCD, and the output of the comparator is connected to a fill and spill reference CCD, which also feeds back a charge to the summing CCD. The comparator output signal is an oversampled digitized version of the analog signal sampled by the input CCD. The comparator output signal is supplied to a low pass digital filter, and a decimator is connected to the output of the digital filter.

Abstract: A programmable data acquisition system including a plurality of input signal channels for receiving a respective input signal during a normal mode of operation is provided. Individual test circuits are used for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in the data acquisition system. An analog-to-digital (A/D) converter system, such as delta-sigma modulators and decimation filters having a selectable decimation ratio, allows for supplying quantized electrical signals at a predetermined rate. The A/D converter is responsive to any signals carried in the plurality of signal channels as selected by the individual test circuits. A control unit allows for supplying respective control signals to the test circuits and to the converter system.