Abstract: A technique to reduce worst-case power drawn by a circuit. The technique utilizes one or more first XOR circuits that receive one or more data signals in a first format and provide them to one or more second XOR circuits in a second format. The second XOR circuits provide data signal outputs in the first format. The XOR circuits are clocked by signals other than the data signals.

Abstract: An apparatus for reducing worst-case power consumption. The apparatus includes a first signal that has signal transitions. A circuit path is provided for transmitting a second signal through buffered circuit sections. Logic circuitry is coupled to the circuit path and to the first signal. The logic circuitry uses the first signal to reduce a sum of signal transitions of the second signal as the second signal propagates from one buffered section of the circuit path to another buffered section of the circuit path in order to reduce worst-case power consumption.

Abstract: An apparatus for reducing worst-case power consumption. The apparatus includes a first signal that has signal transitions. A circuit path is provided for transmitting a second signal through buffered circuit sections. Logic circuitry is coupled to the circuit path and to the first signal. The logic circuitry uses the first signal to reduce a sum of signal transitions of the second signal as the second signal propagates from one buffered section of the circuit path to another buffered section of the circuit path in order to reduce worst-case power consumption.

Abstract: A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative to one another so as to provide a predetermined electrical impedance and may be arranged to carry electrical signals as transmission lines. A dielectric spacer (36) may be disposed between the first and second bus conductors to provide the spacing. Contact regions (24) of the first and second conductors (22a, 22b) may provide compliant coupling regions for the socket (14). The contact regions (24) of the first bus conductor (22a) may be positioned within the socket (14) so as to contact a lead disposed on a first side of a circuit element (16) and the contact regions (24) of the second bus conductor (22b) may be positioned within the socket (14) so as to contact the lead disposed on the second side of the circuit element (16).