Abstract: A combined scalar and vector processing system is provided including a scalar XI directory which records the lines currently being stored into by the scalar processors and vector store register devices (VSR) which record lines currently being stored into by vector processors wherein both vector and scalar XI requests are compared to those addresses stored in the vector store register devices. If there is a compare at a VSR, any responses normally provided from the scalar XI directory are held until the vector store register device receives a release signal from the vector processor indicating said vector processor is finished to thereby prevent the scalar processors from fetching invalid data.

Abstract: A two-level multiple bit error correction scheme includes at the first level a memory chip with a memory error detection capability that produces a chip error signal (CES) when it detects errors in the bits leaving that chip and at the second level an off-chip ECC facility which interprets generated syndrome bits and chip error signals in order to determine which bits are bad. There are two types of codes distinguished by the absence or presence of parity bits. The use of parity bits allows for the detection of single bit errors in data read from the chip. Therefore, the CES is active only for detected multiple bit errors. Chips not using parity bits are less expensive, but the CES must be active for both single bit and multiple bit errors.

Abstract: An improved arbitration system is disclosed for arbitrating signals at a plurality of input nodes to output nodes where each input node can access any output node. The system includes a FIFO (first-in-first-out) input queue for each node and means for arbitrating the top of each queue for providing the arbitrated output to a given node and means when the top of the input queue has no request for a given node arbitrating the requests from the next to the top entry of the input queues and providing the data from the next to top entry associated with the arbitrated request to the given node.

Abstract: A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.

Abstract: A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

Abstract: A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).