Patents by Inventor Donald Wayne Plass

Donald Wayne Plass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compact SRAM cell layout for implementing one-port or two-port operation
    Patent number: 6737685
    Abstract: Compact static random access memory (SRAM) cell layouts are provided for implementing one-port and two-port operation. The SRAM cell layouts include a plurality of field effect transistors (FETs). The plurality of FETs defines a storage cell and a pair of wordline FETs coupled to the storage cell. Each of the plurality of FETs has a device structure extending in a single direction. The device structure of each of the plurality of FETs includes a diffusion layer, a polysilicon layer and first metal layer. A local interconnect connects the diffusion layer, the polysilicon layer and the first metal layer. Each of the pair of wordline FETs having a gate input connected to a wordline. The wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: May 18, 2004
    Assignee: International Business Machines Corporation
    Inventors: Anthony Gus Aipperspach, Donald Wayne Plass
  • Compact SRAM cell layout for implementing one-port or two-port operation
    Publication number: 20030133322
    Abstract: Compact static random access memory (SRAM) cell layouts are provided for implementing one-port and two-port operation. The SRAM cell layouts include a plurality of field effect transistors (FETs). The plurality of FETs defines a storage cell and a pair of wordline FETs coupled to the storage cell. Each of the plurality of FETs has a device structure extending in a single direction. The device structure of each of the plurality of FETs includes a diffusion layer, a polysilicon layer and first metal layer. A local interconnect connects the diffusion layer, the polysilicon layer and the first metal layer. Each of the pair of wordline FETs having a gate input connected to a wordline. The wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 17, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES COPORATION
    Inventors: Anthony Gus Aipperspach, Donald Wayne Plass