Patents by Inventor Donald Westmoreland

Donald Westmoreland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8609221
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Patent number: 8518275
    Abstract: Methods for fabricating sub-lithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland
  • Patent number: 8404124
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Publication number: 20120138570
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Application
    Filed: February 14, 2012
    Publication date: June 7, 2012
    Inventors: Dan B. Millward, Donald Westmoreland
  • Patent number: 8123962
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Patent number: 8114301
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland
  • Publication number: 20100279062
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Publication number: 20090274887
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventors: Dan B. Millward, Donald Westmoreland
  • Publication number: 20080311347
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 18, 2008
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Patent number: 7250367
    Abstract: An ALD method includes exposing a substrate to a first precursor including a plurality of different ligands, chemisorbing a precursor monolayer on the substrate, and reacting a second precursor with the precursor monolayer to yield a product monolayer. A surface reactive ligand exhibits a chemisorption affinity that exceeds the chemisorption affinity exhibited by a gas reactive ligand. Another deposition method includes exposing a substrate to a precursor containing an amino and/or imino ligand and a halide ligand and depositing a layer. The precursor exhibits a volatility that exceeds the volatility with a halide ligand taking the place of each amino and/or imino ligand. The precursor exhibits a thermal stability that exceeds the thermal stability with an amino and/or imino ligand taking the place of each halide ligand. The layer may exhibit less halogen content than with a halide ligand taking the place of each amino and/or imino ligand.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Donald Westmoreland, Eugene P. Marsh, Stefan Uhlenbrock
  • Publication number: 20070148932
    Abstract: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
    Type: Application
    Filed: August 20, 2004
    Publication date: June 28, 2007
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Garo Derderian, Donald Westmoreland, Stefan Uhlenbrook
  • Publication number: 20070045856
    Abstract: Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 1, 2007
    Inventors: Brian Vaartstra, Donald Westmoreland
  • Publication number: 20060261040
    Abstract: A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes an oxidizing agent.
    Type: Application
    Filed: July 27, 2006
    Publication date: November 23, 2006
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Rita Klein, Nishant Sinha, Gundu Sabde, Stefan Uhlenbrock, Donald Westmoreland
  • Publication number: 20060163200
    Abstract: A method of removing an oxide layer from an article. The article may be located in a reaction chamber into which an interhalogen compound reactive with the oxide layer is introduced. A temperature of the reaction chamber may be modified so as to remove the oxide layer. The interhalogen compound may form volatile by-product gases upon reaction with the oxide layer. Unreacted interhalogen compound and volatile by-product gases may then be removed from the reaction chamber.
    Type: Application
    Filed: March 23, 2006
    Publication date: July 27, 2006
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej Sandhu, Donald Westmoreland
  • Publication number: 20060139561
    Abstract: The present invention describes thick film photolithographic molds, methods of making thick film photolithographic molds, and methods of using thick film photolithographic molds to form spacers on a substrate. The thick film photolithographic molds preferably comprise an epoxy bisphenol A novolac resin. The present invention also describes sol gel spacers comprising sodium silicates and potassium silicates. The thick film photolithographic molds and sol gel spacers of the present invention can be used in flat panel displays, such as field emission displays and plasma displays.
    Type: Application
    Filed: February 17, 2006
    Publication date: June 29, 2006
    Inventors: James Hofmann, Brian Vaartstra, Brenda Kraus, Donald Westmoreland
  • Publication number: 20060070574
    Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.
    Type: Application
    Filed: September 1, 2005
    Publication date: April 6, 2006
    Inventors: Garo Derderian, Cem Basceri, Donald Westmoreland
  • Publication number: 20060046521
    Abstract: An ALD method includes exposing a substrate to a first precursor including a plurality of different ligands, chemisorbing a precursor monolayer on the substrate, and reacting a second precursor with the precursor monolayer to yield a product monolayer. A surface reactive ligand exhibits a chemisorption affinity that exceeds the chemisorption affinity exhibited by a gas reactive ligand. Another deposition method includes exposing a substrate to a precursor containing an amino and/or imino ligand and a halide ligand and depositing a layer. The precursor exhibits a volatility that exceeds the volatility with a halide ligand taking the place of each amino and/or imino ligand. The precursor exhibits a thermal stability that exceeds the thermal stability with an amino and/or imino ligand taking the place of each halide ligand. The layer may exhibit less halogen content than with a halide ligand taking the place of each amino and/or imino ligand.
    Type: Application
    Filed: September 1, 2004
    Publication date: March 2, 2006
    Inventors: Brian Vaartstra, Donald Westmoreland, Eugene Marsh, Stefan Uhlenbrock
  • Publication number: 20060040480
    Abstract: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
    Type: Application
    Filed: August 20, 2004
    Publication date: February 23, 2006
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Garo Derderian, Donald Westmoreland, Stefan Uhlenbrook
  • Publication number: 20050287819
    Abstract: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposit ion process and one or more precursor compounds that include organo-amine ligands and one or more precursor compounds that include organo-oxide ligands.
    Type: Application
    Filed: August 31, 2005
    Publication date: December 29, 2005
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brian Vaartstra, Donald Westmoreland
  • Publication number: 20050255698
    Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.
    Type: Application
    Filed: June 7, 2005
    Publication date: November 17, 2005
    Inventors: Gurtej Sandhu, Donald Westmoreland