Abstract: An object-oriented processor and method of operating such a processor are disclosed. According to the method, in response to receiving a first instruction that references a first object having both data and at least a first method associated therewith, an address of the first method is calculated. In addition, at least one pointer is cached that indicates (possibly together with other pointers) the address of the first method. In response to receipt of a subsequent second instruction that references a second object having both data and one or more methods associated therewith, where the one or more methods include the first method, the address of a second method associated with the second object is determined by reference to the cached pointer. In a preferred embodiment of the present invention, the first and second methods comprise the same method, and the cached pointer indicates the entry point of that single method.

Abstract: A method and apparatus for assisting garbage collection process within a Java virtual machine are disclosed. A virtual object heap and a physical object heap are provided within the Java virtual machine, with the virtual object heap considerably larger than the physical object heap. Objects from Java applications are allocated within the virtual object heap. Each address of the allocated objects within the virtual object heap is translated into an address of a location within the physical object heap. Garbage collection is performed in the virtual object heap only when a total number of objects within the virtual object heap has reached a predetermined threshold.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.