Patents by Inventor Donald William Schmidt
Donald William Schmidt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012731Abstract: A computer-implemented method for detecting anomalies in computing systems includes measuring activity metrics associated with accessing resources of the system by several users. Further, condensed diagnostic data is generated by grouping the users into buckets based on bucket and user attributes, and aggregating the activity metrics across all users in each bucket. Bucket contents are recorded during system's use, during which, analytic embedded data is generated for anomaly detection. The generating includes, for each bucket, capturing the activity metrics for an exceptional user in each bucket without aggregation at a next time interval.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Inventors: Benjamin P. Segal, Donald William Schmidt, Erik Richter Altman
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Patent number: 11829790Abstract: A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.Type: GrantFiled: October 20, 2021Date of Patent: November 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
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Patent number: 11822493Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.Type: GrantFiled: June 25, 2021Date of Patent: November 21, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bernd Nerz, Marco Kraemer, Christoph Raisch, Donald William Schmidt, Peter Dana Driever
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Patent number: 11741032Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.Type: GrantFiled: June 25, 2021Date of Patent: August 29, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bernd Nerz, Marco Kraemer, Christoph Raisch, Donald William Schmidt, Peter Dana Driever
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Patent number: 11734037Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.Type: GrantFiled: September 23, 2021Date of Patent: August 22, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marco Kraemer, Christoph Raisch, Bernd Nerz, Donald William Schmidt, Matthias Klein, Sascha Junghans, Peter Dana Driever
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Patent number: 11620244Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.Type: GrantFiled: September 22, 2021Date of Patent: April 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
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Patent number: 11593153Abstract: An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.Type: GrantFiled: December 13, 2021Date of Patent: February 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marco Kraemer, Christoph Raisch, Donald William Schmidt, Bernd Nerz, Frank Siegfried Lehnert, Peter Dana Driever
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Patent number: 11314538Abstract: An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.Type: GrantFiled: November 6, 2020Date of Patent: April 26, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Bernd Nerz, Donald William Schmidt, Peter Dana Driever
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Publication number: 20220100557Abstract: An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Inventors: Marco Kraemer, Christoph Raisch, Donald William Schmidt, Bernd Nerz, Frank Siegfried Lehnert, Peter Dana Driever
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Patent number: 11269794Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.Type: GrantFiled: February 13, 2020Date of Patent: March 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
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Patent number: 11256538Abstract: An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.Type: GrantFiled: December 30, 2020Date of Patent: February 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marco Kraemer, Christoph Raisch, Donald William Schmidt, Bernd Nerz, Frank Siegfried Lehnert, Peter Dana Driever
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Patent number: 11249776Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.Type: GrantFiled: February 13, 2020Date of Patent: February 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marco Kraemer, Christoph Raisch, Bernd Nerz, Donald William Schmidt, Matthias Klein, Sascha Junghans, Peter Dana Driever
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Patent number: 11249927Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.Type: GrantFiled: April 20, 2021Date of Patent: February 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Frank Siegfried Lehnert, Peter Dana Driever
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Patent number: 11243791Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.Type: GrantFiled: February 13, 2020Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
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Publication number: 20220035644Abstract: A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.Type: ApplicationFiled: October 20, 2021Publication date: February 3, 2022Inventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
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Publication number: 20220012198Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.Type: ApplicationFiled: September 22, 2021Publication date: January 13, 2022Inventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
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Publication number: 20220004412Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.Type: ApplicationFiled: September 23, 2021Publication date: January 6, 2022Inventors: Marco Kraemer, Christoph Raisch, Bernd Nerz, Donald William Schmidt, Matthias Klein, Sascha Junghans, Peter Dana Driever
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Patent number: 11182269Abstract: A computer-implemented method for proactive change verification is provided. Aspects include analyzing runtime execution characteristics from a plurality of base activity metrics and a plurality of experimental activity metrics and creating a plurality of activity pairs wherein each activity pair comprises a base activity metric and its corresponding experimental activity metric. Aspects also include identifying significant activity pairs from the plurality of activity pairs wherein the experimental activity significantly deviates from its corresponding base activity and classifying significant activity pairs by deviation type. Aspects further include sorting activity pairs by their impact and removing activity pairs that have an impact of less than a threshold amount, wherein the threshold amount is based on the deviation type.Type: GrantFiled: October 1, 2019Date of Patent: November 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Rosa, Donald William Schmidt, Qi Liang, Gui Yu Jiang
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Publication number: 20210318973Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Inventors: Bernd Nerz, Marco Kraemer, Christoph Raisch, Donald William Schmidt, Peter Dana Driever
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Patent number: 11138139Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.Type: GrantFiled: February 13, 2020Date of Patent: October 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bernd Nerz, Marco Kraemer, Christoph Raisch, Donald William Schmidt, Peter Dana Driever