Abstract: Provided herein are antibodies that bind to a peptide of an N-terminally ubiquitinated polypeptide and methods of screening for such antibodies. Also provided herein are detection and enrichment methods using such antibodies for detecting or enriching a peptide of an N-terminally ubiquitinated polypeptide.

Abstract: A method and apparatus using a clock generator with sequential logic to align the phase of a first clock generated on a receiving integrated circuit (IC) chip to a second clock received by the receiving IC chip. One embodiment of the invention involves a method for aligning the phase of a first clock relative to the phase of a second clock, wherein the first clock is provided by a clock generator in a data processing system. The method includes sampling the second clock with a sampling clock, detecting an edge on the second clock, and stretching the first clock to align the phase of the first clock relative to the phase of the second clock. A second embodiment of the invention involves a data processing system including a transmitting chip, a receiving chip, and a clock generator for aligning the phase of a first clock relative to the phase of a second clock, wherein the second clock is received by the receiving chip.

Abstract: A pressure control apparatus for use in a bed including a pressurized air source, an inflatable air sack, and an independently inflatable cell located adjacent the inflatable air sack. A controller is operable to regulate the pressure in the air sack and to independently alternately pressurize and vent the inflatable cell at a selected frequency.

Abstract: An apparatus and method for an improved asynchronous communication channel between a transmitter and a receiver having separate clocks. The invention provides a simple implementation that solves both the overflow and the underflow problem using the same mechanism, and reduces complexity by elimination of the control split between the two clock domains. A first embodiment of the invention is a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, including a buffer that can store a number of packets greater than an ideal number of packets.

Abstract: A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system.

Abstract: Variable power eyeglasses of many shapes can be manufactured having a frame, a pair of lens assemblies and a linear actuation mechanism. Each lens assembly includes: a rigid substrate; a membrane support spaced from the rigid substrate; a flexible seal extending between the rigid substrate and the membrane support, where the flexible seal acts as a hinge at a first section and acts as a spring by allowing relative motion between the rigid substrate and the membrane support at a second section; a transparent elastomeric membrane sealed around a periphery to the membrane support; and a transparent liquid filling the space between the rigid substrate and the membrane forming a liquid lens. The linear actuation mechanism causes relative motion between the membrane and the rigid substrate so that both optical and prismatic power of the liquid lens changes by varying a force applied to the flexible sealing means at the second section.

Abstract: A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.

Abstract: A scheme for improving the decoding time of macroinstruction opcodes in a programmed computer is provided. By having a direct Instruction Jump Table responding to macroinstructions and a pipelined Address Jump Table responding to the same macroinstructions simultaneously, larger sequences of microinstructions are decoded in a minimum number of microcycles, thus resulting in a faster operating programmed computer.

Abstract: A tow crimping apparatus that includes a pair of advancing rolls associated with a crimping chamber is provided with a movable roll to permit controlled loading of the nip between the rolls. The controlled loading is accomplished through a pressure chamber linked to the movable roll and having a restricter in the pressure supply line to the pressure chamber.