Abstract: A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor.

Abstract: Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory.An additional pair of bit positions are provided with each SR to receive lookahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block.During each subsequent address translation, the loaded lookahead bits are outgated while the block address is being read from an SR. The lookahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit.The lookahead bits are handled by parallel high-speed circuits which operate faster than the larger translation circuits handling the block address being read from the SR.

Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key.The maximum extendable size of the memory can substantially exceed the maximum addressing capability of any program, which is determined by the relocatable addressability obtained through any stack of segmentation registers.

Abstract: Common logic in a peripheral device control unit responds to a serially propagated poll signal from I/O control logic, or channel, along with a coded signal identifying either a poll for a cycle steal request or a poll for an interrupt request having one of several priorities. The poll signal received will be captured or propagated to following control units dependent upon whether the control unit has requested a cycle steal transfer, or has requested an interrupt at the priority level indicated by the coded signal accompanying the poll signal. Proper functioning of poll capture or propagation is possible even though one of the control units is physically removed from the serial chain of control units.